forked from OSchip/llvm-project
[AArch64] Allocate the modified and used regs only once per function.
llvm-svn: 259510
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@ -88,6 +88,9 @@ struct AArch64LoadStoreOpt : public MachineFunctionPass {
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const TargetRegisterInfo *TRI;
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const TargetRegisterInfo *TRI;
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const AArch64Subtarget *Subtarget;
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const AArch64Subtarget *Subtarget;
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// Track which registers have been modified and used.
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BitVector ModifiedRegs, UsedRegs;
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// Scan the instructions looking for a load/store that can be combined
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// Scan the instructions looking for a load/store that can be combined
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// with the current instruction into a load/store pair.
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// with the current instruction into a load/store pair.
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// Return the matching instruction if one is found, else MBB->end().
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// Return the matching instruction if one is found, else MBB->end().
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@ -1015,9 +1018,8 @@ bool AArch64LoadStoreOpt::findMatchingStore(
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// Track which registers have been modified and used between the first insn
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// Track which registers have been modified and used between the first insn
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// and the second insn.
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// and the second insn.
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BitVector ModifiedRegs, UsedRegs;
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ModifiedRegs.reset();
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ModifiedRegs.resize(TRI->getNumRegs());
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UsedRegs.reset();
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UsedRegs.resize(TRI->getNumRegs());
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for (unsigned Count = 0; MBBI != E && Count < Limit;) {
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for (unsigned Count = 0; MBBI != E && Count < Limit;) {
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--MBBI;
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--MBBI;
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@ -1096,9 +1098,8 @@ AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
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// Track which registers have been modified and used between the first insn
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// Track which registers have been modified and used between the first insn
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// (inclusive) and the second insn.
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// (inclusive) and the second insn.
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BitVector ModifiedRegs, UsedRegs;
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ModifiedRegs.reset();
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ModifiedRegs.resize(TRI->getNumRegs());
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UsedRegs.reset();
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UsedRegs.resize(TRI->getNumRegs());
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// Remember any instructions that read/write memory between FirstMI and MI.
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// Remember any instructions that read/write memory between FirstMI and MI.
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SmallVector<MachineInstr *, 4> MemInsns;
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SmallVector<MachineInstr *, 4> MemInsns;
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@ -1378,9 +1379,8 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnForward(
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// Track which registers have been modified and used between the first insn
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// Track which registers have been modified and used between the first insn
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// (inclusive) and the second insn.
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// (inclusive) and the second insn.
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BitVector ModifiedRegs, UsedRegs;
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ModifiedRegs.reset();
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ModifiedRegs.resize(TRI->getNumRegs());
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UsedRegs.reset();
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UsedRegs.resize(TRI->getNumRegs());
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++MBBI;
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++MBBI;
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for (; MBBI != E; ++MBBI) {
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for (; MBBI != E; ++MBBI) {
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MachineInstr *MI = MBBI;
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MachineInstr *MI = MBBI;
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@ -1428,9 +1428,8 @@ MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
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// Track which registers have been modified and used between the first insn
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// Track which registers have been modified and used between the first insn
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// (inclusive) and the second insn.
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// (inclusive) and the second insn.
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BitVector ModifiedRegs, UsedRegs;
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ModifiedRegs.reset();
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ModifiedRegs.resize(TRI->getNumRegs());
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UsedRegs.reset();
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UsedRegs.resize(TRI->getNumRegs());
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--MBBI;
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--MBBI;
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for (; MBBI != B; --MBBI) {
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for (; MBBI != B; --MBBI) {
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MachineInstr *MI = MBBI;
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MachineInstr *MI = MBBI;
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@ -1784,6 +1783,12 @@ bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
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TII = static_cast<const AArch64InstrInfo *>(Subtarget->getInstrInfo());
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TII = static_cast<const AArch64InstrInfo *>(Subtarget->getInstrInfo());
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TRI = Subtarget->getRegisterInfo();
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TRI = Subtarget->getRegisterInfo();
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// Resize the modified and used register bitfield trackers. We do this once
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// per function and then clear the bitfield each time we optimize a load or
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// store.
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ModifiedRegs.resize(TRI->getNumRegs());
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UsedRegs.resize(TRI->getNumRegs());
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bool Modified = false;
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bool Modified = false;
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bool enableNarrowLdOpt = enableNarrowLdMerge(Fn);
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bool enableNarrowLdOpt = enableNarrowLdMerge(Fn);
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for (auto &MBB : Fn)
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for (auto &MBB : Fn)
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