forked from OSchip/llvm-project
llvm-mc/AsmParser: Implement automatic classification of RegisterClass operands.
- This drops us to 123 ambiguous instructions (previously ~500) on X86. llvm-svn: 78636
This commit is contained in:
Daniel Dunbar
parent
dd4103b55b
commit
bb98db2d21
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@ -30,9 +30,22 @@
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subl $256, %eax
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// FIXME: Check that this matches XOR64ri8
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// RUN: grep {MCInst(opcode=.*, operands=.reg:19, reg:0, val:1.)} %t
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xorq $1, %eax
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// RUN: grep {MCInst(opcode=.*, operands=.reg:80, reg:0, val:1.)} %t
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xorq $1, %rax
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// FIXME: Check that this matches XOR64ri32
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// RUN: grep {MCInst(opcode=.*, operands=.reg:19, reg:0, val:256.)} %t
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xorq $256, %eax
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// RUN: grep {MCInst(opcode=.*, operands=.reg:80, reg:0, val:256.)} %t
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xorq $256, %rax
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// FIXME: Check that this matches SUB8rr
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// RUN: grep {MCInst(opcode=.*, operands=.reg:5, reg:0, reg:2.)} %t
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subb %al, %bl
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// FIXME: Check that this matches SUB16rr
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// RUN: grep {MCInst(opcode=.*, operands=.reg:8, reg:0, reg:3.)} %t
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subw %ax, %bx
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// FIXME: Check that this matches SUB32rr
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// RUN: grep {MCInst(opcode=.*, operands=.reg:21, reg:0, reg:19.)} %t
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subl %eax, %ebx
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@ -282,19 +282,29 @@ namespace {
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/// class of operands which can be matched.
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struct ClassInfo {
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enum ClassInfoKind {
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Invalid = 0, ///< Invalid kind, for use as a sentinel value.
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Token, ///< The class for a particular token.
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Register, ///< A register class.
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UserClass0 ///< The (first) user defined class, subsequent user defined
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/// classes are UserClass0+1, and so on.
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/// Invalid kind, for use as a sentinel value.
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Invalid = 0,
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/// The class for a particular token.
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Token,
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/// The (first) register class, subsequent register classes are
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/// RegisterClass0+1, and so on.
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RegisterClass0,
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/// The (first) user defined class, subsequent user defined classes are
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/// UserClass0+1, and so on.
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UserClass0 = 1<<16
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};
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/// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
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/// N) for the Nth user defined class.
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unsigned Kind;
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/// SuperClass - The super class, or 0.
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ClassInfo *SuperClass;
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/// SuperClasses - The super classes of this class. Note that for simplicities
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/// sake user operands only record their immediate super class, while register
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/// operands include all superclasses.
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std::vector<ClassInfo*> SuperClasses;
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/// Name - The full class name, suitable for use in an enum.
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std::string Name;
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@ -308,30 +318,67 @@ struct ClassInfo {
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std::string ValueName;
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/// PredicateMethod - The name of the operand method to test whether the
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/// operand matches this class; this is not valid for Token kinds.
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/// operand matches this class; this is not valid for Token or register kinds.
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std::string PredicateMethod;
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/// RenderMethod - The name of the operand method to add this operand to an
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/// MCInst; this is not valid for Token kinds.
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/// MCInst; this is not valid for Token or register kinds.
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std::string RenderMethod;
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/// isRegisterClass() - Check if this is a register class.
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bool isRegisterClass() const {
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return Kind >= RegisterClass0 && Kind < UserClass0;
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}
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/// isUserClass() - Check if this is a user defined class.
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bool isUserClass() const {
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return Kind >= UserClass0;
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}
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/// getRootClass - Return the root class of this one.
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const ClassInfo *getRootClass() const {
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const ClassInfo *CI = this;
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while (CI->SuperClass)
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CI = CI->SuperClass;
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return CI;
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/// isRelatedTo - Check whether this class is "related" to \arg RHS. Classes
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/// are related if they are in the same class hierarchy.
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bool isRelatedTo(const ClassInfo &RHS) const {
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// Tokens are only related to tokens.
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if (Kind == Token || RHS.Kind == Token)
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return Kind == Token && RHS.Kind == Token;
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// Registers are only related to registers.
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if (isRegisterClass() || RHS.isRegisterClass())
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return isRegisterClass() && RHS.isRegisterClass();
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// Otherwise we have two users operands; they are related if they are in the
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// same class hierarchy.
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assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
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const ClassInfo *Root = this;
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while (!Root->SuperClasses.empty())
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Root = Root->SuperClasses.front();
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const ClassInfo *RHSRoot = this;
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while (!RHSRoot->SuperClasses.empty())
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RHSRoot = RHSRoot->SuperClasses.front();
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return Root == RHSRoot;
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}
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/// isSubsetOf - Test whether this class is a subset of \arg RHS;
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bool isSubsetOf(const ClassInfo &RHS) const {
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// This is a subset of RHS if it is the same class...
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if (this == &RHS)
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return true;
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// ... or if any of its super classes are a subset of RHS.
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for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(),
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ie = SuperClasses.end(); it != ie; ++it)
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if ((*it)->isSubsetOf(RHS))
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return true;
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return false;
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}
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/// operator< - Compare two classes.
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bool operator<(const ClassInfo &RHS) const {
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// Incompatible kinds are comparable for classes in disjoint hierarchies.
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if (Kind != RHS.Kind && getRootClass() != RHS.getRootClass())
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// Unrelated classes can be ordered by kind.
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if (!isRelatedTo(RHS))
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return Kind < RHS.Kind;
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switch (Kind) {
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@ -344,12 +391,8 @@ struct ClassInfo {
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return ValueName < RHS.ValueName;
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default:
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// This class preceeds the RHS if the RHS is a super class.
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for (ClassInfo *Parent = SuperClass; Parent; Parent = Parent->SuperClass)
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if (Parent == &RHS)
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return true;
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return false;
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// This class preceeds the RHS if it is a proper subset of the RHS.
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return this != &RHS && isSubsetOf(RHS);
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}
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}
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};
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@ -446,12 +489,15 @@ public:
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/// The information on the instruction to match.
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std::vector<InstructionInfo*> Instructions;
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/// Map of Register records to their class information.
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std::map<Record*, ClassInfo*> RegisterClasses;
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private:
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/// Map of token to class information which has already been constructed.
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std::map<std::string, ClassInfo*> TokenClasses;
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/// The ClassInfo instance for registers.
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ClassInfo *TheRegisterClass;
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/// Map of RegisterClass records to their class information.
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std::map<Record*, ClassInfo*> RegisterClassClasses;
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/// Map of AsmOperandClass records to their class information.
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std::map<Record*, ClassInfo*> AsmOperandClasses;
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@ -464,6 +510,14 @@ private:
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ClassInfo *getOperandClass(const StringRef &Token,
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const CodeGenInstruction::OperandInfo &OI);
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/// BuildRegisterClasses - Build the ClassInfo* instances for register
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/// classes.
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void BuildRegisterClasses(CodeGenTarget &Target);
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/// BuildOperandClasses - Build the ClassInfo* instances for user defined
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/// operand classes.
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void BuildOperandClasses(CodeGenTarget &Target);
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public:
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/// BuildInfo - Construct the various tables used during matching.
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void BuildInfo(CodeGenTarget &Target);
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@ -522,7 +576,6 @@ ClassInfo *AsmMatcherInfo::getTokenClass(const StringRef &Token) {
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if (!Entry) {
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Entry = new ClassInfo();
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Entry->Kind = ClassInfo::Token;
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Entry->SuperClass = 0;
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Entry->ClassName = "Token";
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Entry->Name = "MCK_" + getEnumNameForToken(Token);
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Entry->ValueName = Token;
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@ -537,8 +590,16 @@ ClassInfo *AsmMatcherInfo::getTokenClass(const StringRef &Token) {
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ClassInfo *
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AsmMatcherInfo::getOperandClass(const StringRef &Token,
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const CodeGenInstruction::OperandInfo &OI) {
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if (OI.Rec->isSubClassOf("RegisterClass"))
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return TheRegisterClass;
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if (OI.Rec->isSubClassOf("RegisterClass")) {
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ClassInfo *CI = RegisterClassClasses[OI.Rec];
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if (!CI) {
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PrintError(OI.Rec->getLoc(), "register class has no class info!");
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throw std::string("ERROR: Missing register class!");
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}
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return CI;
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}
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assert(OI.Rec->isSubClassOf("Operand") && "Unexpected operand!");
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Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass");
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@ -552,23 +613,105 @@ AsmMatcherInfo::getOperandClass(const StringRef &Token,
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return CI;
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}
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void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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// Build the assembly match class information.
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void AsmMatcherInfo::BuildRegisterClasses(CodeGenTarget &Target) {
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std::vector<CodeGenRegisterClass> RegisterClasses;
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std::vector<CodeGenRegister> Registers;
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// Construct the "Reg" class.
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//
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// FIXME: This needs to dice up the RegisterClass instances.
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ClassInfo *RegClass = TheRegisterClass = new ClassInfo();
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RegClass->Kind = ClassInfo::Register;
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RegClass->SuperClass = 0;
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RegClass->ClassName = "Reg";
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RegClass->Name = "MCK_Reg";
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RegClass->ValueName = "<register class>";
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RegClass->PredicateMethod = "isReg";
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RegClass->RenderMethod = "addRegOperands";
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Classes.push_back(RegClass);
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RegisterClasses = Target.getRegisterClasses();
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Registers = Target.getRegisters();
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// Build info for the user defined assembly operand classes.
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// The register sets used for matching.
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std::set< std::set<Record*> > RegisterSets;
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// Gather the defined sets.
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for (std::vector<CodeGenRegisterClass>::iterator it = RegisterClasses.begin(),
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ie = RegisterClasses.end(); it != ie; ++it)
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RegisterSets.insert(std::set<Record*>(it->Elements.begin(),
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it->Elements.end()));
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// Introduce derived sets where necessary (when a register does not determine
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// a unique register set class), and build the mapping of registers to the set
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// they should classify to.
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std::map<Record*, std::set<Record*> > RegisterMap;
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for (std::vector<CodeGenRegister>::iterator it = Registers.begin(),
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ie = Registers.end(); it != ie; ++it) {
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CodeGenRegister &CGR = *it;
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// Compute the intersection of all sets containing this register.
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std::set<Record*> ContainingSet;
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for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
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ie = RegisterSets.end(); it != ie; ++it) {
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if (!it->count(CGR.TheDef))
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continue;
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if (ContainingSet.empty()) {
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ContainingSet = *it;
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} else {
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std::set<Record*> Tmp;
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std::swap(Tmp, ContainingSet);
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std::insert_iterator< std::set<Record*> > II(ContainingSet,
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ContainingSet.begin());
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std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(),
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II);
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}
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}
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if (!ContainingSet.empty()) {
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RegisterSets.insert(ContainingSet);
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RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
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}
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}
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// Construct the register classes.
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std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses;
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unsigned Index = 0;
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for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
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ie = RegisterSets.end(); it != ie; ++it, ++Index) {
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ClassInfo *CI = new ClassInfo();
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CI->Kind = ClassInfo::RegisterClass0 + Index;
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CI->ClassName = "Reg" + utostr(Index);
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CI->Name = "MCK_Reg" + utostr(Index);
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CI->ValueName = "";
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CI->PredicateMethod = ""; // unused
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CI->RenderMethod = "addRegOperands";
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Classes.push_back(CI);
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RegisterSetClasses.insert(std::make_pair(*it, CI));
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}
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// Find the superclasses; we could compute only the subgroup lattice edges,
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// but there isn't really a point.
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for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
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ie = RegisterSets.end(); it != ie; ++it) {
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ClassInfo *CI = RegisterSetClasses[*it];
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for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
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ie2 = RegisterSets.end(); it2 != ie2; ++it2)
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if (*it != *it2 &&
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std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
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CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
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}
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// Name the register classes which correspond to a user defined RegisterClass.
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for (std::vector<CodeGenRegisterClass>::iterator it = RegisterClasses.begin(),
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ie = RegisterClasses.end(); it != ie; ++it) {
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ClassInfo *CI = RegisterSetClasses[std::set<Record*>(it->Elements.begin(),
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it->Elements.end())];
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if (CI->ValueName.empty()) {
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CI->ClassName = it->getName();
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CI->Name = "MCK_" + it->getName();
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CI->ValueName = it->getName();
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} else
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CI->ValueName = CI->ValueName + "," + it->getName();
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RegisterClassClasses.insert(std::make_pair(it->TheDef, CI));
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}
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// Populate the map for individual registers.
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for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(),
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ie = RegisterMap.end(); it != ie; ++it)
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this->RegisterClasses[it->first] = RegisterSetClasses[it->second];
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}
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void AsmMatcherInfo::BuildOperandClasses(CodeGenTarget &Target) {
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std::vector<Record*> AsmOperands;
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AsmOperands = Records.getAllDerivedDefinitions("AsmOperandClass");
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unsigned Index = 0;
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@ -579,12 +722,13 @@ void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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Init *Super = (*it)->getValueInit("SuperClass");
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if (DefInit *DI = dynamic_cast<DefInit*>(Super)) {
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CI->SuperClass = AsmOperandClasses[DI->getDef()];
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if (!CI->SuperClass)
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ClassInfo *SC = AsmOperandClasses[DI->getDef()];
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if (!SC)
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PrintError((*it)->getLoc(), "Invalid super class reference!");
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else
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CI->SuperClasses.push_back(SC);
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} else {
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assert(dynamic_cast<UnsetInit*>(Super) && "Unexpected SuperClass field!");
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CI->SuperClass = 0;
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}
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CI->ClassName = (*it)->getValueAsString("Name");
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CI->Name = "MCK_" + CI->ClassName;
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@ -613,6 +757,14 @@ void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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AsmOperandClasses[*it] = CI;
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Classes.push_back(CI);
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}
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}
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void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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// Build info for the register classes.
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BuildRegisterClasses(Target);
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// Build info for the user defined assembly operand classes.
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BuildOperandClasses(Target);
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// Build the instruction information.
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for (std::map<std::string, CodeGenInstruction>::const_iterator
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@ -746,7 +898,15 @@ static void EmitConvertToMCInst(CodeGenTarget &Target,
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for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex)
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Signature += "Imp";
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Signature += Op.Class->ClassName;
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// Registers are always converted the same, don't duplicate the conversion
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// function based on them.
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//
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// FIXME: We could generalize this based on the render method, if it
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// mattered.
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if (Op.Class->isRegisterClass())
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Signature += "Reg";
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else
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Signature += Op.Class->ClassName;
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Signature += utostr(Op.OperandInfo->MINumOperands);
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Signature += "_" + utostr(MIOperandList[i].second);
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@ -820,7 +980,7 @@ static void EmitMatchClassEnumeration(CodeGenTarget &Target,
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OS << " " << CI.Name << ", // ";
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if (CI.Kind == ClassInfo::Token) {
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OS << "'" << CI.ValueName << "'\n";
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} else if (CI.Kind == ClassInfo::Register) {
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} else if (CI.isRegisterClass()) {
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if (!CI.ValueName.empty())
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OS << "register class '" << CI.ValueName << "'\n";
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else
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@ -837,34 +997,59 @@ static void EmitMatchClassEnumeration(CodeGenTarget &Target,
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/// EmitClassifyOperand - Emit the function to classify an operand.
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static void EmitClassifyOperand(CodeGenTarget &Target,
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std::vector<ClassInfo*> &Infos,
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AsmMatcherInfo &Info,
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raw_ostream &OS) {
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OS << "static MatchClassKind ClassifyOperand("
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<< Target.getName() << "Operand &Operand) {\n";
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// Classify tokens.
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OS << " if (Operand.isToken())\n";
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OS << " return MatchTokenString(Operand.getToken());\n\n";
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for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
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ie = Infos.end(); it != ie; ++it) {
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// Classify registers.
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//
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// FIXME: Don't hardcode isReg, getReg.
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OS << " if (Operand.isReg()) {\n";
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OS << " switch (Operand.getReg()) {\n";
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OS << " default: return InvalidMatchClass;\n";
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for (std::map<Record*, ClassInfo*>::iterator
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it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
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it != ie; ++it)
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OS << " case " << Target.getName() << "::"
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<< it->first->getName() << ": return " << it->second->Name << ";\n";
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OS << " }\n";
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OS << " }\n\n";
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// Classify user defined operands.
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for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
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ie = Info.Classes.end(); it != ie; ++it) {
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ClassInfo &CI = **it;
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if (CI.Kind != ClassInfo::Token) {
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OS << " // '" << CI.ClassName << "' class";
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if (CI.SuperClass) {
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||||
OS << ", subclass of '" << CI.SuperClass->ClassName << "'";
|
||||
assert(CI < *CI.SuperClass && "Invalid class relation!");
|
||||
if (!CI.isUserClass())
|
||||
continue;
|
||||
|
||||
OS << " // '" << CI.ClassName << "' class";
|
||||
if (!CI.SuperClasses.empty()) {
|
||||
OS << ", subclass of ";
|
||||
for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) {
|
||||
if (i) OS << ", ";
|
||||
OS << "'" << CI.SuperClasses[i]->ClassName << "'";
|
||||
assert(CI < *CI.SuperClasses[i] && "Invalid class relation!");
|
||||
}
|
||||
OS << "\n";
|
||||
|
||||
OS << " if (Operand." << CI.PredicateMethod << "()) {\n";
|
||||
|
||||
// Validate subclass relationships.
|
||||
if (CI.SuperClass)
|
||||
OS << " assert(Operand." << CI.SuperClass->PredicateMethod
|
||||
<< "() && \"Invalid class relationship!\");\n";
|
||||
|
||||
OS << " return " << CI.Name << ";\n";
|
||||
OS << " }\n\n";
|
||||
}
|
||||
OS << "\n";
|
||||
|
||||
OS << " if (Operand." << CI.PredicateMethod << "()) {\n";
|
||||
|
||||
// Validate subclass relationships.
|
||||
if (!CI.SuperClasses.empty()) {
|
||||
for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i)
|
||||
OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod
|
||||
<< "() && \"Invalid class relationship!\");\n";
|
||||
}
|
||||
|
||||
OS << " return " << CI.Name << ";\n";
|
||||
OS << " }\n\n";
|
||||
}
|
||||
OS << " return InvalidMatchClass;\n";
|
||||
OS << "}\n\n";
|
||||
|
|
@ -892,7 +1077,7 @@ static void EmitIsSubclass(CodeGenTarget &Target,
|
|||
ie = Infos.end(); it != ie; ++it) {
|
||||
ClassInfo &B = **it;
|
||||
|
||||
if (&A != &B && A.getRootClass() == B.getRootClass() && A < B)
|
||||
if (&A != &B && A.isSubsetOf(B))
|
||||
SuperClasses.push_back(B.Name);
|
||||
}
|
||||
|
||||
|
|
@ -902,15 +1087,15 @@ static void EmitIsSubclass(CodeGenTarget &Target,
|
|||
OS << "\n case " << A.Name << ":\n";
|
||||
|
||||
if (SuperClasses.size() == 1) {
|
||||
OS << " return B == " << SuperClasses.back() << ";\n\n";
|
||||
OS << " return B == " << SuperClasses.back() << ";\n";
|
||||
continue;
|
||||
}
|
||||
|
||||
OS << " switch (B) {\n";
|
||||
OS << " default: return false;\n";
|
||||
OS << " switch (B) {\n";
|
||||
OS << " default: return false;\n";
|
||||
for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i)
|
||||
OS << " case " << SuperClasses[i] << ": return true;\n";
|
||||
OS << " }\n\n";
|
||||
OS << " case " << SuperClasses[i] << ": return true;\n";
|
||||
OS << " }\n";
|
||||
}
|
||||
}
|
||||
OS << " }\n";
|
||||
|
|
@ -1154,7 +1339,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
|||
EmitMatchTokenString(Target, Info.Classes, OS);
|
||||
|
||||
// Emit the routine to classify an operand.
|
||||
EmitClassifyOperand(Target, Info.Classes, OS);
|
||||
EmitClassifyOperand(Target, Info, OS);
|
||||
|
||||
// Emit the subclass predicate routine.
|
||||
EmitIsSubclass(Target, Info.Classes, OS);
|
||||
|
|
|
|||
Loading…
Reference in New Issue