forked from OSchip/llvm-project
Apparently, the "regType" and "regClass" used in the Sparc backend are not both
correct: empirically, "regType" is wrong for a number of registers. Thus, one can only rely on the "regClass" to figure out what kind of register one is dealing with. This change switches to using only "regClass" and adds a few extra DEBUG() print statements and a few clean-ups in comments and code, mostly minor. llvm-svn: 7103
This commit is contained in:
Misha Brukman
parent
2b30ecdb77
commit
bb95605448
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@ -334,9 +334,9 @@ bool SparcV9CodeEmitter::isFPInstr(MachineInstr &MI) {
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unsigned fakeReg = MO.getReg(), realReg, regClass, regType;
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regType = TM.getRegInfo().getRegType(fakeReg);
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// At least map fakeReg into its class
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fakeReg = TM.getRegInfo().getClassRegNum(fakeReg, regClass);
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if (regClass == UltraSparcRegInfo::FPSingleRegType ||
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regClass == UltraSparcRegInfo::FPDoubleRegType)
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// fakeReg = TM.getRegInfo().getClassRegNum(fakeReg, regClass);
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if (regType == UltraSparcRegInfo::FPSingleRegType ||
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regType == UltraSparcRegInfo::FPDoubleRegType)
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return true;
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}
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}
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@ -344,9 +344,9 @@ bool SparcV9CodeEmitter::isFPInstr(MachineInstr &MI) {
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}
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unsigned
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SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg, unsigned regClass,
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SparcV9CodeEmitter::getRealRegNumByType(unsigned fakeReg, unsigned regType,
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MachineInstr &MI) {
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switch (regClass) {
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switch (regType) {
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case UltraSparcRegInfo::IntRegType: {
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// Sparc manual, p31
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static const unsigned IntRegMap[] = {
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@ -354,10 +354,8 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg, unsigned regClass,
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8, 9, 10, 11, 12, 13, 15,
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// "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
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16, 17, 18, 19, 20, 21, 22, 23,
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// "i0", "i1", "i2", "i3", "i4", "i5",
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24, 25, 26, 27, 28, 29,
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// "i6", "i7",
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30, 31,
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// "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
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24, 25, 26, 27, 28, 29, 30, 31,
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// "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
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0, 1, 2, 3, 4, 5, 6, 7,
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// "o6"
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@ -368,15 +366,17 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg, unsigned regClass,
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break;
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}
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case UltraSparcRegInfo::FPSingleRegType: {
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DEBUG(std::cerr << "FP single reg: " << fakeReg << "\n");
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return fakeReg;
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}
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case UltraSparcRegInfo::FPDoubleRegType: {
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DEBUG(std::cerr << "FP double reg: " << fakeReg << "\n");
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return fakeReg;
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}
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case UltraSparcRegInfo::FloatCCRegType: {
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/* These are laid out %fcc0 - %fcc3 => 0 - 3, so are correct */
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DEBUG(std::cerr << "FP CC reg: " << fakeReg << "\n");
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return fakeReg;
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}
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case UltraSparcRegInfo::IntCCRegType: {
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static const unsigned FPInstrIntCCReg[] = { 6 /* xcc */, 4 /* icc */ };
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@ -384,11 +384,13 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg, unsigned regClass,
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if (isFPInstr(MI)) {
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assert(fakeReg < sizeof(FPInstrIntCCReg)/sizeof(FPInstrIntCCReg[0])
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&& "Int CC register out of bounds for FPInstr IntCCReg map");
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&& "FP CC register out of bounds for FPInstr IntCCReg map");
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DEBUG(std::cerr << "FP instr, IntCC reg: " << FPInstrIntCCReg[fakeReg] << "\n");
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return FPInstrIntCCReg[fakeReg];
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} else {
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assert(fakeReg < sizeof(IntInstrIntCCReg)/sizeof(IntInstrIntCCReg[0])
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&& "Int CC register out of bounds for IntInstr IntCCReg map");
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DEBUG(std::cerr << "FP instr, IntCC reg: " << IntInstrIntCCReg[fakeReg] << "\n");
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return IntInstrIntCCReg[fakeReg];
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}
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}
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@ -398,6 +400,60 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg, unsigned regClass,
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}
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}
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unsigned
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SparcV9CodeEmitter::getRealRegNumByClass(unsigned fakeReg, unsigned regClass,
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MachineInstr &MI) {
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switch (regClass) {
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case UltraSparcRegInfo::IntRegClassID: {
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// Sparc manual, p31
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static const unsigned IntRegMap[] = {
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// "o0", "o1", "o2", "o3", "o4", "o5", "o7",
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8, 9, 10, 11, 12, 13, 15,
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// "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
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16, 17, 18, 19, 20, 21, 22, 23,
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// "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
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24, 25, 26, 27, 28, 29, 30, 31,
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// "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
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0, 1, 2, 3, 4, 5, 6, 7,
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// "o6"
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14
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};
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return IntRegMap[fakeReg];
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break;
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}
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case UltraSparcRegInfo::FloatRegClassID: {
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DEBUG(std::cerr << "FP reg: " << fakeReg << "\n");
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return fakeReg;
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}
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case UltraSparcRegInfo::IntCCRegClassID: {
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static const unsigned FPInstrIntCCReg[] = { 6 /* xcc */, 4 /* icc */ };
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static const unsigned IntInstrIntCCReg[] = { 2 /* xcc */, 0 /* icc */ };
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if (isFPInstr(MI)) {
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assert(fakeReg < sizeof(FPInstrIntCCReg)/sizeof(FPInstrIntCCReg[0])
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&& "FP CC register out of bounds for FPInstr IntCCReg map");
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DEBUG(std::cerr << "FP instr, IntCC reg: " << FPInstrIntCCReg[fakeReg] << "\n");
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return FPInstrIntCCReg[fakeReg];
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} else {
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assert(fakeReg < sizeof(IntInstrIntCCReg)/sizeof(IntInstrIntCCReg[0])
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&& "Int CC register out of bounds for IntInstr IntCCReg map");
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DEBUG(std::cerr << "FP instr, IntCC reg: " << IntInstrIntCCReg[fakeReg] << "\n");
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return IntInstrIntCCReg[fakeReg];
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}
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}
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case UltraSparcRegInfo::FloatCCRegClassID: {
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/* These are laid out %fcc0 - %fcc3 => 0 - 3, so are correct */
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DEBUG(std::cerr << "FP CC reg: " << fakeReg << "\n");
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return fakeReg;
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}
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default:
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assert(0 && "Invalid unified register number in getRegType");
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return fakeReg;
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}
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}
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int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
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MachineOperand &MO) {
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int64_t rv = 0; // Return value; defaults to 0 for unhandled cases
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@ -477,19 +533,22 @@ int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
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} else if (MO.isPhysicalRegister() ||
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MO.getType() == MachineOperand::MO_CCRegister)
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{
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// This is necessary because the Sparc doesn't actually lay out registers
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// in the real fashion -- it skips those that it chooses not to allocate,
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// i.e. those that are the SP, etc.
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unsigned fakeReg = MO.getReg(), realReg, regClass, regType;
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regType = TM.getRegInfo().getRegType(fakeReg);
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// This is necessary because the Sparc backend doesn't actually lay out
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// registers in the real fashion -- it skips those that it chooses not to
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// allocate, i.e. those that are the FP, SP, etc.
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unsigned fakeReg = MO.getAllocatedRegNum(), regClass, regType;
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unsigned realRegByClass; //realRegByType,
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const TargetRegInfo &RI = TM.getRegInfo();
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DEBUG(std::cerr << std::dec << "LLC: " << fakeReg << " => "
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<< RI.getUnifiedRegName(fakeReg) << "\n");
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regType = RI.getRegType(fakeReg);
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// At least map fakeReg into its class
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fakeReg = TM.getRegInfo().getClassRegNum(fakeReg, regClass);
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// Find the real register number for use in an instruction
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/////realReg = getRealRegNum(fakeReg, regClass, MI);
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realReg = getRealRegNum(fakeReg, regType, MI);
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DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] = "
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<< realReg << "\n");
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rv = realReg;
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fakeReg = RI.getClassRegNum(fakeReg, regClass);
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//realRegByType = getRealRegNumByType(fakeReg, regType, MI);
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realRegByClass = getRealRegNumByClass(fakeReg, regClass, MI);
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DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] = by class: "
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<< realRegByClass << "\n");
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rv = realRegByClass;
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} else if (MO.isImmediate()) {
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rv = MO.getImmedValue();
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DEBUG(std::cerr << "immed: " << rv << "\n");
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@ -561,8 +620,7 @@ bool SparcV9CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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{
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Constant *C = (Constant*)*I;
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unsigned idx = MCP.getConstantPoolIndex(C);
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DEBUG(std::cerr << "Mapping constant 0x" << (intptr_t)C << " to "
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<< idx << "\n");
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DEBUG(std::cerr << "Constant[" << idx << "] = 0x" << (intptr_t)C << "\n");
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ConstantMap[C] = idx;
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}
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MCE.emitConstantPool(&MCP);
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@ -571,31 +629,24 @@ bool SparcV9CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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emitBasicBlock(*I);
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MCE.finishFunction(MF);
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DEBUG(std::cerr << "Finishing function " << MF.getFunction()->getName()
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<< "\n");
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DEBUG(std::cerr << "Finishing fn " << MF.getFunction()->getName() << "\n");
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ConstantMap.clear();
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for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
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long Location = BBLocations[BBRefs[i].first];
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unsigned *Ref = BBRefs[i].second.first;
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MachineInstr *MI = BBRefs[i].second.second;
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DEBUG(std::cerr << "Fixup @" << std::hex << Ref << " to " << Location
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<< " in instr: " << std::dec << *MI << "\n");
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}
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// Resolve branches to BasicBlocks for the entire function
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for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
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long Location = BBLocations[BBRefs[i].first];
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unsigned *Ref = BBRefs[i].second.first;
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MachineInstr *MI = BBRefs[i].second.second;
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DEBUG(std::cerr << "attempting to resolve BB: " << i << "\n");
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DEBUG(std::cerr << "Fixup @ " << std::hex << Ref << " to 0x" << Location
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<< " in instr: " << std::dec << *MI);
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for (unsigned ii = 0, ee = MI->getNumOperands(); ii != ee; ++ii) {
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MachineOperand &op = MI->getOperand(ii);
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if (op.isPCRelativeDisp()) {
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// the instruction's branch target is made such that it branches to
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// PC + (br target * 4), so undo that arithmetic here:
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// PC + (branchTarget * 4), so undo that arithmetic here:
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// Location is the target of the branch
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// Ref is the location of the instruction, and hence the PC
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unsigned branchTarget = (Location - (long)Ref) >> 2;
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int64_t branchTarget = (Location - (long)Ref) >> 2;
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// Save the flags.
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bool loBits32=false, hiBits32=false, loBits64=false, hiBits64=false;
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if (op.opLoBits32()) { loBits32=true; }
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@ -43,12 +43,14 @@ public:
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private:
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int64_t getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
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unsigned getValueBit(int64_t Val, unsigned bit);
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inline unsigned getValueBit(int64_t Val, unsigned bit);
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void emitBasicBlock(MachineBasicBlock &MBB);
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void* getGlobalAddress(GlobalValue *V, MachineInstr &MI,
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bool isPCRelative);
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bool isFPInstr(MachineInstr &MI);
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unsigned getRealRegNum(unsigned fakeReg, unsigned regClass,
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unsigned getRealRegNumByType(unsigned fakeReg, unsigned regType,
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MachineInstr &MI);
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unsigned getRealRegNumByClass(unsigned fakeReg, unsigned regClass,
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MachineInstr &MI);
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};
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