forked from OSchip/llvm-project
Create a pattern for the "trap" instruction.
llvm-svn: 187863
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4e06f0d106
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@ -148,6 +148,20 @@ class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
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let Inst{4-0} = funct;
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}
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class FRRBreak16<dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin>
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{
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bits<6> Code;
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bits<5> funct;
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let Opcode = 0b11101;
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let funct = 0b00101;
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let Inst{10-5} = Code;
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let Inst{4-0} = funct;
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}
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//
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// For conversion functions.
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//
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@ -292,6 +292,11 @@ class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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!strconcat(asmstr, "\t$rx, $ry"), [], itin> {
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}
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class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> :
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FRRBreak16<(outs), (ins), asmstr, [], itin> {
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let Code=0;
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}
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class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry"), [], itin> {
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@ -574,6 +579,13 @@ def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
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//
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def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
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//
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//Format: BREAK immediate
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// Purpose: Breakpoint
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// To cause a Breakpoint exception.
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def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>;
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//
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// Format: BTEQZ offset MIPS16e
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// Purpose: Branch on T Equal to Zero (Extended)
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@ -1796,3 +1808,6 @@ def : Mips16Pat<(i32 (extloadi8 addr16:$src)),
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(LbuRxRyOffMemX16 addr16:$src)>;
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def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
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(LhuRxRyOffMemX16 addr16:$src)>;
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def: Mips16Pat<(trap), (Break16)>;
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@ -0,0 +1,13 @@
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic < %s | FileCheck %s -check-prefix=pic
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declare void @llvm.trap()
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; Function Attrs: nounwind optsize readnone
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define i32 @main() {
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entry:
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call void @llvm.trap()
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unreachable
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; pic: break 0
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ret i32 0
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}
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