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[llvm] Use llvm::reverse (NFC)

This commit is contained in:
Kazu Hirata 2021-12-12 16:13:49 -08:00
parent 9ad5969b5e
commit bb6447a78c
11 changed files with 37 additions and 46 deletions
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3
llvm/lib/CodeGen/CodeGenPrepare.cpp
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@ -6852,8 +6852,7 @@ bool CodeGenPrepare::optimizeSelectInst(SelectInst *SI) {
// Use reverse iterator because later select may use the value of the
// earlier select, and we need to propagate value through earlier select
// to get the PHI operand.
for (auto It = ASI.rbegin(); It != ASI.rend(); ++It) {
SelectInst *SI = *It;
for (SelectInst *SI : llvm::reverse(ASI)) {
// The select itself is replaced with a PHI Node.
PHINode *PN = PHINode::Create(SI->getType(), 2, "", &EndBlock->front());
PN->takeName(SI);

4
llvm/lib/CodeGen/MachineFunction.cpp
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@ -771,8 +771,8 @@ MCSymbol *MachineFunction::addLandingPad(MachineBasicBlock *LandingPad) {
void MachineFunction::addCatchTypeInfo(MachineBasicBlock *LandingPad,
ArrayRef<const GlobalValue *> TyInfo) {
LandingPadInfo &LP = getOrCreateLandingPadInfo(LandingPad);
for (unsigned N = TyInfo.size(); N; --N)
LP.TypeIds.push_back(getTypeIDFor(TyInfo[N - 1]));
for (const GlobalValue *GV : llvm::reverse(TyInfo))
LP.TypeIds.push_back(getTypeIDFor(GV));
}
void MachineFunction::addFilterTypeInfo(MachineBasicBlock *LandingPad,

6
llvm/lib/CodeGen/MachinePipeliner.cpp
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@ -2874,10 +2874,8 @@ void SMSchedule::finalizeSchedule(SwingSchedulerDAG *SSD) {
++stage) {
std::deque<SUnit *> &cycleInstrs =
ScheduledInstrs[cycle + (stage * InitiationInterval)];
for (std::deque<SUnit *>::reverse_iterator I = cycleInstrs.rbegin(),
E = cycleInstrs.rend();
I != E; ++I)
ScheduledInstrs[cycle].push_front(*I);
for (SUnit *SU : llvm::reverse(cycleInstrs))
ScheduledInstrs[cycle].push_front(SU);
}
}

3
llvm/lib/CodeGen/MachineTraceMetrics.cpp
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@ -984,8 +984,7 @@ addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
const MachineBasicBlock *DefMBB = DefMI->getParent();
// Reg is live-in to all blocks in Trace that follow DefMBB.
for (unsigned i = Trace.size(); i; --i) {
const MachineBasicBlock *MBB = Trace[i-1];
for (const MachineBasicBlock *MBB : llvm::reverse(Trace)) {
if (MBB == DefMBB)
return;
TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()];

4
llvm/lib/CodeGen/RDFGraph.cpp
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@ -1500,8 +1500,8 @@ void DataFlowGraph::buildPhis(BlockRefsMap &PhiM, RegisterSet &AllRefs,
// Erase from MaxRefs all elements in the closure.
auto Begin = MaxRefs.begin();
for (unsigned i = ClosureIdx.size(); i != 0; --i)
MaxRefs.erase(Begin + ClosureIdx[i-1]);
for (unsigned Idx : llvm::reverse(ClosureIdx))
MaxRefs.erase(Begin + Idx);
}
}

8
llvm/lib/CodeGen/ScheduleDAG.cpp
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@ -618,8 +618,8 @@ std::vector<int> ScheduleDAGTopologicalSort::GetSubGraph(const SUnit &StartSU,
do {
const SUnit *SU = WorkList.back();
WorkList.pop_back();
for (int I = SU->Succs.size()-1; I >= 0; --I) {
const SUnit *Succ = SU->Succs[I].getSUnit();
for (const SDep &SD : llvm::reverse(SU->Succs)) {
const SUnit *Succ = SD.getSUnit();
unsigned s = Succ->NodeNum;
// Edges to non-SUnits are allowed but ignored (e.g. ExitSU).
if (Succ->isBoundaryNode())
@ -652,8 +652,8 @@ std::vector<int> ScheduleDAGTopologicalSort::GetSubGraph(const SUnit &StartSU,
do {
const SUnit *SU = WorkList.back();
WorkList.pop_back();
for (int I = SU->Preds.size()-1; I >= 0; --I) {
const SUnit *Pred = SU->Preds[I].getSUnit();
for (const SDep &SD : llvm::reverse(SU->Preds)) {
const SUnit *Pred = SD.getSUnit();
unsigned s = Pred->NodeNum;
// Edges to non-SUnits are allowed but ignored (e.g. EntrySU).
if (Pred->isBoundaryNode())

10
llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp
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@ -131,15 +131,15 @@ bool StackMapLiveness::calculateLiveness(MachineFunction &MF) {
bool HasStackMap = false;
// Reverse iterate over all instructions and add the current live register
// set to an instruction if we encounter a patchpoint instruction.
for (auto I = MBB.rbegin(), E = MBB.rend(); I != E; ++I) {
if (I->getOpcode() == TargetOpcode::PATCHPOINT) {
addLiveOutSetToMI(MF, *I);
for (MachineInstr &MI : llvm::reverse(MBB)) {
if (MI.getOpcode() == TargetOpcode::PATCHPOINT) {
addLiveOutSetToMI(MF, MI);
HasChanged = true;
HasStackMap = true;
++NumStackMaps;
}
LLVM_DEBUG(dbgs() << " " << LiveRegs << " " << *I);
LiveRegs.stepBackward(*I);
LLVM_DEBUG(dbgs() << " " << LiveRegs << " " << MI);
LiveRegs.stepBackward(MI);
}
++NumBBsVisited;
if (!HasStackMap)

15
llvm/lib/CodeGen/WinEHPrepare.cpp
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@ -573,9 +573,7 @@ void llvm::calculateClrEHStateNumbers(const Function *Fn,
const auto *CatchSwitch = cast<CatchSwitchInst>(Pad);
int CatchState = -1, FollowerState = -1;
SmallVector<const BasicBlock *, 4> CatchBlocks(CatchSwitch->handlers());
for (auto CBI = CatchBlocks.rbegin(), CBE = CatchBlocks.rend();
CBI != CBE; ++CBI, FollowerState = CatchState) {
const BasicBlock *CatchBlock = *CBI;
for (const BasicBlock *CatchBlock : llvm::reverse(CatchBlocks)) {
// Create the entry for this catch with the appropriate handler
// properties.
const auto *Catch = cast<CatchPadInst>(CatchBlock->getFirstNonPHI());
@ -591,6 +589,7 @@ void llvm::calculateClrEHStateNumbers(const Function *Fn,
Worklist.emplace_back(I, CatchState);
// Remember this catch's state.
FuncInfo.EHPadStateMap[Catch] = CatchState;
FollowerState = CatchState;
}
// Associate the catchswitch with the state of its first catch.
assert(CatchSwitch->getNumHandlers());
@ -601,11 +600,9 @@ void llvm::calculateClrEHStateNumbers(const Function *Fn,
// Step two: record the TryParentState of each state. For cleanuppads that
// don't have cleanuprets, we may need to infer this from their child pads,
// so visit pads in descendant-most to ancestor-most order.
for (auto Entry = FuncInfo.ClrEHUnwindMap.rbegin(),
End = FuncInfo.ClrEHUnwindMap.rend();
Entry != End; ++Entry) {
for (ClrEHUnwindMapEntry &Entry : llvm::reverse(FuncInfo.ClrEHUnwindMap)) {
const Instruction *Pad =
Entry->Handler.get<const BasicBlock *>()->getFirstNonPHI();
Entry.Handler.get<const BasicBlock *>()->getFirstNonPHI();
// For most pads, the TryParentState is the state associated with the
// unwind dest of exceptional exits from it.
const BasicBlock *UnwindDest;
@ -615,7 +612,7 @@ void llvm::calculateClrEHStateNumbers(const Function *Fn,
// that's not the unwind dest of exceptions escaping the catch. Those
// cases were already assigned a TryParentState in the first pass, so
// skip them.
if (Entry->TryParentState != -1)
if (Entry.TryParentState != -1)
continue;
// Otherwise, get the unwind dest from the catchswitch.
UnwindDest = Catch->getCatchSwitch()->getUnwindDest();
@ -692,7 +689,7 @@ void llvm::calculateClrEHStateNumbers(const Function *Fn,
UnwindDestState = FuncInfo.EHPadStateMap[UnwindDest->getFirstNonPHI()];
}
Entry->TryParentState = UnwindDestState;
Entry.TryParentState = UnwindDestState;
}
// Step three: transfer information from pads to invokes.

16
llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
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@ -995,8 +995,8 @@ bool DeadCodeElimination::runOnNode(MachineDomTreeNode *N) {
MachineBasicBlock *B = N->getBlock();
std::vector<MachineInstr*> Instrs;
for (auto I = B->rbegin(), E = B->rend(); I != E; ++I)
Instrs.push_back(&*I);
for (MachineInstr &MI : llvm::reverse(*B))
Instrs.push_back(&MI);
for (auto MI : Instrs) {
unsigned Opc = MI->getOpcode();
@ -3155,20 +3155,20 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
// if that instruction could potentially be moved to the front of the loop:
// the output of the loop cannot be used in a non-shuffling instruction
// in this loop.
for (auto I = C.LB->rbegin(), E = C.LB->rend(); I != E; ++I) {
if (I->isTerminator())
for (MachineInstr &MI : llvm::reverse(*C.LB)) {
if (MI.isTerminator())
continue;
if (I->isPHI())
if (MI.isPHI())
break;
RegisterSet Defs;
HBS::getInstrDefs(*I, Defs);
HBS::getInstrDefs(MI, Defs);
if (Defs.count() != 1)
continue;
Register DefR = Defs.find_first();
if (!DefR.isVirtual())
continue;
if (!isBitShuffle(&*I, DefR))
if (!isBitShuffle(&MI, DefR))
continue;
bool BadUse = false;
@ -3198,7 +3198,7 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
if (BadUse)
continue;
ShufIns.push_back(&*I);
ShufIns.push_back(&MI);
}
// Partition the list of shuffling instructions into instruction groups,

4
llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
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@ -1445,8 +1445,8 @@ bool HexagonGenInsert::removeDeadCode(MachineDomTreeNode *N) {
MachineBasicBlock *B = N->getBlock();
std::vector<MachineInstr*> Instrs;
for (auto I = B->rbegin(), E = B->rend(); I != E; ++I)
Instrs.push_back(&*I);
for (MachineInstr &MI : llvm::reverse(*B))
Instrs.push_back(&MI);
for (MachineInstr *MI : Instrs) {
unsigned Opc = MI->getOpcode();

10
llvm/lib/Target/X86/X86FixupBWInsts.cpp
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@ -457,14 +457,12 @@ void FixupBWInstPass::processBasicBlock(MachineFunction &MF,
OptForSize = MF.getFunction().hasOptSize() ||
llvm::shouldOptimizeForSize(&MBB, PSI, MBFI);
for (auto I = MBB.rbegin(); I != MBB.rend(); ++I) {
MachineInstr *MI = &*I;
if (MachineInstr *NewMI = tryReplaceInstr(MI, MBB))
MIReplacements.push_back(std::make_pair(MI, NewMI));
for (MachineInstr &MI : llvm::reverse(MBB)) {
if (MachineInstr *NewMI = tryReplaceInstr(&MI, MBB))
MIReplacements.push_back(std::make_pair(&MI, NewMI));
// We're done with this instruction, update liveness for the next one.
LiveRegs.stepBackward(*MI);
LiveRegs.stepBackward(MI);
}
while (!MIReplacements.empty()) {