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Compile time improvements to VirtRegRewriter. 

This change to VirtRegRewriter::addMBBLiveIns adds live-in registers for each
MachineBasicBlock's LiveIns set without isLiveIn checks as they are being added
because doing so is expensive. After all live-in registers are added, the LiveIn
vectors are sorted and uniqued.

llvm-svn: 238008
This commit is contained in:
Puyan Lotfi 2015-05-22 08:11:26 +00:00
parent 263b27997d
commit bb457b973d
2 changed files with 19 additions and 7 deletions
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15
llvm/include/llvm/CodeGen/MachineBasicBlock.h
View File

@ -315,9 +315,18 @@ public:
// LiveIn management methods. // LiveIn management methods.
/// addLiveIn - Add the specified register as a live in. Note that it /// Adds the specified register as a live in. Note that it is an error to add
/// is an error to add the same register to the same set more than once. /// the same register to the same set more than once unless the intention is
void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); } /// to call sortUniqueLiveIns after all registers are added.
void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); }
/// Sorts and uniques the LiveIns vector. It can be significantly faster to do
/// this than repeatedly calling isLiveIn before calling addLiveIn for every
/// LiveIn insertion.
void sortUniqueLiveIns() {
std::sort(LiveIns.begin(), LiveIns.end());
LiveIns.erase(std::unique(LiveIns.begin(), LiveIns.end()), LiveIns.end());
}
/// Add PhysReg as live in to this block, and ensure that there is a copy of /// Add PhysReg as live in to this block, and ensure that there is a copy of
/// PhysReg to a virtual register of class RC. Return the virtual register /// PhysReg to a virtual register of class RC. Return the virtual register

11
llvm/lib/CodeGen/VirtRegMap.cpp
View File

@ -264,8 +264,7 @@ void VirtRegRewriter::addMBBLiveIns() {
if ((SubRegLaneMask & S.LaneMask) == 0) if ((SubRegLaneMask & S.LaneMask) == 0)
continue; continue;
for (unsigned i = 0, e = LiveIn.size(); i != e; ++i) { for (unsigned i = 0, e = LiveIn.size(); i != e; ++i) {
if (!LiveIn[i]->isLiveIn(SubReg)) LiveIn[i]->addLiveIn(SubReg);
LiveIn[i]->addLiveIn(SubReg);
} }
} }
LiveIn.clear(); LiveIn.clear();
@ -277,12 +276,16 @@ void VirtRegRewriter::addMBBLiveIns() {
if (!Indexes->findLiveInMBBs(Seg.start, Seg.end, LiveIn)) if (!Indexes->findLiveInMBBs(Seg.start, Seg.end, LiveIn))
continue; continue;
for (unsigned i = 0, e = LiveIn.size(); i != e; ++i) for (unsigned i = 0, e = LiveIn.size(); i != e; ++i)
if (!LiveIn[i]->isLiveIn(PhysReg)) LiveIn[i]->addLiveIn(PhysReg);
LiveIn[i]->addLiveIn(PhysReg);
LiveIn.clear(); LiveIn.clear();
} }
} }
} }
// Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
// each MBB's LiveIns set before calling addLiveIn on them.
for (MachineBasicBlock &MBB : *MF)
MBB.sortUniqueLiveIns();
} }
void VirtRegRewriter::rewrite() { void VirtRegRewriter::rewrite() {