maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

revert rL344609: [InstCombine] try harder to form select from logic ops 

I noticed a missing check and added it at rL344610, but there actually
are codegen tests that will fail without that, so I'll edit those and
submit a fixed patch with more tests.

llvm-svn: 344612
This commit is contained in:
Sanjay Patel 2018-10-16 15:26:08 +00:00
parent 2927071750
commit bb3dd34e62
4 changed files with 53 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

67
llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
View File

@ -1831,29 +1831,14 @@ static bool areInverseVectorBitmasks(Constant *C1, Constant *C2) {
/// We have an expression of the form (A & C) | (B & D). If A is a scalar or
/// vector composed of all-zeros or all-ones values and is the bitwise 'not' of
/// B, it can be used as the condition operand of a select instruction.
Value *InstCombiner::getSelectCondition(Value *A, Value *B) {
// Step 1: We need 0 or all-1's bitmasks.
static Value *getSelectCondition(Value *A, Value *B,
InstCombiner::BuilderTy &Builder) {
// If these are scalars or vectors of i1, A can be used directly.
Type *Ty = A->getType();
if (Ty->isIntOrIntVectorTy() &&
ComputeNumSignBits(A) != Ty->getScalarSizeInBits())
return nullptr;
if (match(A, m_Not(m_Specific(B))) && Ty->isIntOrIntVectorTy(1))
return A;
// Step 2: If B is the 'not' value of A, we have our answer.
if (match(A, m_Not(m_Specific(B)))) {
// If these are scalars or vectors of i1, A can be used directly.
if (Ty->isIntOrIntVectorTy(1))
return A;
return Builder.CreateTrunc(A, CmpInst::makeCmpResultType(Ty));
}
// If both operands are constants, see if the constants are inverse bitmasks.
Constant *AConst, *BConst;
if (match(A, m_Constant(AConst)) && match(B, m_Constant(BConst)))
if (AConst == ConstantExpr::getNot(BConst))
return Builder.CreateZExtOrTrunc(A, CmpInst::makeCmpResultType(Ty));
// Look for more complex patterns. The 'not' op may be hidden behind various
// casts. Look through sexts and bitcasts to find the booleans.
// If A and B are sign-extended, look through the sexts to find the booleans.
Value *Cond;
Value *NotB;
if (match(A, m_SExt(m_Value(Cond))) &&
@ -1869,30 +1854,36 @@ Value *InstCombiner::getSelectCondition(Value *A, Value *B) {
if (!Ty->isVectorTy())
return nullptr;
// If both operands are constants, see if the constants are inverse bitmasks.
Constant *AC, *BC;
if (match(A, m_Constant(AC)) && match(B, m_Constant(BC)) &&
areInverseVectorBitmasks(AC, BC)) {
return Builder.CreateZExtOrTrunc(AC, CmpInst::makeCmpResultType(Ty));
}
// If both operands are xor'd with constants using the same sexted boolean
// operand, see if the constants are inverse bitmasks.
// TODO: Use ConstantExpr::getNot()?
if (match(A, (m_Xor(m_SExt(m_Value(Cond)), m_Constant(AConst)))) &&
match(B, (m_Xor(m_SExt(m_Specific(Cond)), m_Constant(BConst)))) &&
if (match(A, (m_Xor(m_SExt(m_Value(Cond)), m_Constant(AC)))) &&
match(B, (m_Xor(m_SExt(m_Specific(Cond)), m_Constant(BC)))) &&
Cond->getType()->isIntOrIntVectorTy(1) &&
areInverseVectorBitmasks(AConst, BConst)) {
AConst = ConstantExpr::getTrunc(AConst, CmpInst::makeCmpResultType(Ty));
return Builder.CreateXor(Cond, AConst);
areInverseVectorBitmasks(AC, BC)) {
AC = ConstantExpr::getTrunc(AC, CmpInst::makeCmpResultType(Ty));
return Builder.CreateXor(Cond, AC);
}
return nullptr;
}
/// We have an expression of the form (A & C) | (B & D). Try to simplify this
/// to "A' ? C : D", where A' is a boolean or vector of booleans.
Value *InstCombiner::matchSelectFromAndOr(Value *A, Value *C, Value *B,
Value *D) {
static Value *matchSelectFromAndOr(Value *A, Value *C, Value *B, Value *D,
InstCombiner::BuilderTy &Builder) {
// The potential condition of the select may be bitcasted. In that case, look
// through its bitcast and the corresponding bitcast of the 'not' condition.
Type *OrigType = A->getType();
A = peekThroughBitcast(A, true);
B = peekThroughBitcast(B, true);
if (Value *Cond = getSelectCondition(A, B)) {
if (Value *Cond = getSelectCondition(A, B, Builder)) {
// ((bc Cond) & C) | ((bc ~Cond) & D) --> bc (select Cond, (bc C), (bc D))
// The bitcasts will either all exist or all not exist. The builder will
// not create unnecessary casts if the types already match.
@ -2243,21 +2234,21 @@ Instruction *InstCombiner::visitOr(BinaryOperator &I) {
// 'or' that it is replacing.
if (Op0->hasOneUse() || Op1->hasOneUse()) {
// (Cond & C) | (~Cond & D) -> Cond ? C : D, and commuted variants.
if (Value *V = matchSelectFromAndOr(A, C, B, D))
if (Value *V = matchSelectFromAndOr(A, C, B, D, Builder))
return replaceInstUsesWith(I, V);
if (Value *V = matchSelectFromAndOr(A, C, D, B))
if (Value *V = matchSelectFromAndOr(A, C, D, B, Builder))
return replaceInstUsesWith(I, V);
if (Value *V = matchSelectFromAndOr(C, A, B, D))
if (Value *V = matchSelectFromAndOr(C, A, B, D, Builder))
return replaceInstUsesWith(I, V);
if (Value *V = matchSelectFromAndOr(C, A, D, B))
if (Value *V = matchSelectFromAndOr(C, A, D, B, Builder))
return replaceInstUsesWith(I, V);
if (Value *V = matchSelectFromAndOr(B, D, A, C))
if (Value *V = matchSelectFromAndOr(B, D, A, C, Builder))
return replaceInstUsesWith(I, V);
if (Value *V = matchSelectFromAndOr(B, D, C, A))
if (Value *V = matchSelectFromAndOr(B, D, C, A, Builder))
return replaceInstUsesWith(I, V);
if (Value *V = matchSelectFromAndOr(D, B, A, C))
if (Value *V = matchSelectFromAndOr(D, B, A, C, Builder))
return replaceInstUsesWith(I, V);
if (Value *V = matchSelectFromAndOr(D, B, C, A))
if (Value *V = matchSelectFromAndOr(D, B, C, A, Builder))
return replaceInstUsesWith(I, V);
}
}

3
llvm/lib/Transforms/InstCombine/InstCombineInternal.h
View File

@ -589,9 +589,6 @@ private:
Value *foldAndOrOfICmpsOfAndWithPow2(ICmpInst *LHS, ICmpInst *RHS,
bool JoinedByAnd, Instruction &CxtI);
Value *matchSelectFromAndOr(Value *A, Value *B, Value *C, Value *D);
Value *getSelectCondition(Value *A, Value *B);
public:
/// Inserts an instruction \p New before instruction \p Old
///

18
llvm/test/Transforms/InstCombine/logical-select.ll
View File

@ -535,9 +535,12 @@ define <4 x i32> @vec_sel_xor_multi_use(<4 x i32> %a, <4 x i32> %b, <4 x i1> %c)
define i32 @allSignBits(i32 %cond, i32 %tval, i32 %fval) {
; CHECK-LABEL: @allSignBits(
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[COND:%.*]], 0
; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[TVAL:%.*]], i32 [[FVAL:%.*]]
; CHECK-NEXT: ret i32 [[TMP2]]
; CHECK-NEXT: [[BITMASK:%.*]] = ashr i32 [[COND:%.*]], 31
; CHECK-NEXT: [[NOT_BITMASK:%.*]] = xor i32 [[BITMASK]], -1
; CHECK-NEXT: [[A1:%.*]] = and i32 [[BITMASK]], [[TVAL:%.*]]
; CHECK-NEXT: [[A2:%.*]] = and i32 [[NOT_BITMASK]], [[FVAL:%.*]]
; CHECK-NEXT: [[SEL:%.*]] = or i32 [[A1]], [[A2]]
; CHECK-NEXT: ret i32 [[SEL]]
;
%bitmask = ashr i32 %cond, 31
%not_bitmask = xor i32 %bitmask, -1
@ -549,9 +552,12 @@ define i32 @allSignBits(i32 %cond, i32 %tval, i32 %fval) {
define <4 x i8> @allSignBits_vec(<4 x i8> %cond, <4 x i8> %tval, <4 x i8> %fval) {
; CHECK-LABEL: @allSignBits_vec(
; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i8> [[COND:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1>
; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i8> [[FVAL:%.*]], <4 x i8> [[TVAL:%.*]]
; CHECK-NEXT: ret <4 x i8> [[TMP2]]
; CHECK-NEXT: [[BITMASK:%.*]] = ashr <4 x i8> [[COND:%.*]], <i8 7, i8 7, i8 7, i8 7>
; CHECK-NEXT: [[NOT_BITMASK:%.*]] = xor <4 x i8> [[BITMASK]], <i8 -1, i8 -1, i8 -1, i8 -1>
; CHECK-NEXT: [[A1:%.*]] = and <4 x i8> [[BITMASK]], [[TVAL:%.*]]
; CHECK-NEXT: [[A2:%.*]] = and <4 x i8> [[NOT_BITMASK]], [[FVAL:%.*]]
; CHECK-NEXT: [[SEL:%.*]] = or <4 x i8> [[A2]], [[A1]]
; CHECK-NEXT: ret <4 x i8> [[SEL]]
;
%bitmask = ashr <4 x i8> %cond, <i8 7, i8 7, i8 7, i8 7>
%not_bitmask = xor <4 x i8> %bitmask, <i8 -1, i8 -1, i8 -1, i8 -1>

18
llvm/test/Transforms/InstCombine/vec_sext.ll
View File

@ -4,9 +4,12 @@
define <4 x i32> @vec_select(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: @vec_select(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[A:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[B:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[A]], <4 x i32> [[SUB]]
; CHECK-NEXT: ret <4 x i32> [[TMP2]]
; CHECK-NEXT: [[B_LOBIT1:%.*]] = ashr <4 x i32> [[B:%.*]], <i32 31, i32 31, i32 31, i32 31>
; CHECK-NEXT: [[T1:%.*]] = xor <4 x i32> [[B_LOBIT1]], <i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: [[T2:%.*]] = and <4 x i32> [[T1]], [[A]]
; CHECK-NEXT: [[T3:%.*]] = and <4 x i32> [[B_LOBIT1]], [[SUB]]
; CHECK-NEXT: [[COND:%.*]] = or <4 x i32> [[T2]], [[T3]]
; CHECK-NEXT: ret <4 x i32> [[COND]]
;
%cmp = icmp slt <4 x i32> %b, zeroinitializer
%sext = sext <4 x i1> %cmp to <4 x i32>
@ -23,9 +26,12 @@ define <4 x i32> @vec_select(<4 x i32> %a, <4 x i32> %b) {
define <4 x i32> @vec_select_alternate_sign_bit_test(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: @vec_select_alternate_sign_bit_test(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[A:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[B:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[SUB]], <4 x i32> [[A]]
; CHECK-NEXT: ret <4 x i32> [[TMP2]]
; CHECK-NEXT: [[B_LOBIT1:%.*]] = ashr <4 x i32> [[B:%.*]], <i32 31, i32 31, i32 31, i32 31>
; CHECK-NEXT: [[B_LOBIT1_NOT:%.*]] = xor <4 x i32> [[B_LOBIT1]], <i32 -1, i32 -1, i32 -1, i32 -1>
; CHECK-NEXT: [[T2:%.*]] = and <4 x i32> [[B_LOBIT1]], [[A]]
; CHECK-NEXT: [[T3:%.*]] = and <4 x i32> [[B_LOBIT1_NOT]], [[SUB]]
; CHECK-NEXT: [[COND:%.*]] = or <4 x i32> [[T2]], [[T3]]
; CHECK-NEXT: ret <4 x i32> [[COND]]
;
%cmp = icmp sgt <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
%sext = sext <4 x i1> %cmp to <4 x i32>