forked from OSchip/llvm-project
[SelectionDAG] Fix incorrect offset when expanding CONCAT_VECTORS.
ExpandVectorBuildThroughStack is also used for CONCAT_VECTORS. However, when calculating the offsets for each of the operands we incorrectly use the element size rather than actual size and thus the stores overlap. Differential Revision: https://reviews.llvm.org/D83303
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llvm
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@ -1390,12 +1390,17 @@ SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
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}
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SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
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assert((Node->getOpcode() == ISD::BUILD_VECTOR ||
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Node->getOpcode() == ISD::CONCAT_VECTORS) &&
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"Unexpected opcode!");
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// We can't handle this case efficiently. Allocate a sufficiently
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// aligned object on the stack, store each element into it, then load
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// aligned object on the stack, store each operand into it, then load
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// the result as a vector.
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// Create the stack frame object.
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EVT VT = Node->getValueType(0);
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EVT EltVT = VT.getVectorElementType();
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EVT MemVT = isa<BuildVectorSDNode>(Node) ? VT.getVectorElementType()
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: Node->getOperand(0).getValueType();
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SDLoc dl(Node);
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SDValue FIPtr = DAG.CreateStackTemporary(VT);
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int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
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@ -1404,7 +1409,7 @@ SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
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// Emit a store of each element to the stack slot.
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SmallVector<SDValue, 8> Stores;
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unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
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unsigned TypeByteSize = MemVT.getSizeInBits() / 8;
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assert(TypeByteSize > 0 && "Vector element type too small for stack store!");
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// Store (in the right endianness) the elements to memory.
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for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
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@ -1417,11 +1422,11 @@ SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
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// If the destination vector element type is narrower than the source
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// element type, only store the bits necessary.
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if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
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if (MemVT.bitsLT(Node->getOperand(i).getValueType()))
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Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
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Node->getOperand(i), Idx,
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PtrInfo.getWithOffset(Offset), EltVT));
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} else
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PtrInfo.getWithOffset(Offset), MemVT));
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else
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Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
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Idx, PtrInfo.getWithOffset(Offset)));
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}
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@ -0,0 +1,38 @@
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; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s
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; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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target triple = "aarch64-unknown-linux-gnu"
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; NOTE: Currently all CONCAT_VECTORS get expanded so there's little point in
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; validating all combinations of vector type.
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define void @concat_vectors_v4i64(<2 x i64> %a, <2 x i64> %b, <4 x i64> *%c.addr) #0 {
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; CHECK-LABEL: concat_vectors_v4i64:
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; CHECK: stp q0, q1, [sp]
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; CHECK: ptrue [[OUT_PG:p[0-9]+]].d, vl4
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; CHECK: mov x[[LO_ADDR:[0-9]+]], sp
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; CHECK: ld1d { z{{[0-9]+}}.d }, [[OUT_PG]]/z, [x[[LO_ADDR]]]
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%concat = shufflevector <2 x i64> %a, <2 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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store <4 x i64> %concat, <4 x i64>* %c.addr
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ret void
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}
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define void @concat_vectors_v8i64(<4 x i64> *%a.addr, <4 x i64> *%b.addr, <8 x i64> *%c.addr) #0 {
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; VBITS_GE_512-LABEL: concat_vectors_v8i64:
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; VBITS_GE_512: ptrue [[IN_PG:p[0-9]+]].d, vl4
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; VBITS_GE_512: ld1d { [[LO:z[0-9]+]].d }, [[IN_PG]]/z, [x0]
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; VBITS_GE_512: ld1d { [[HI:z[0-9]+]].d }, [[IN_PG]]/z, [x1]
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; VBITS_GE_512: mov x[[LO_ADDR:[0-9]+]], sp
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; VBITS_GE_512: orr x[[HI_ADDR:[0-9]+]], x[[LO_ADDR]], #0x20
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; VBITS_GE_512: st1d { [[LO]].d }, [[IN_PG]], [x[[LO_ADDR]]]
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; VBITS_GE_512: st1d { [[HI]].d }, [[IN_PG]], [x[[HI_ADDR]]]
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; VBITS_GE_512: ptrue [[OUT_PG:p[0-9]+]].d, vl8
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; VBITS_GE_512: ld1d { z{{[0-9]+}}.d }, [[OUT_PG]]/z, [x8]
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%a = load <4 x i64>, <4 x i64>* %a.addr
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%b = load <4 x i64>, <4 x i64>* %b.addr
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%concat = shufflevector <4 x i64> %a, <4 x i64> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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store <8 x i64> %concat, <8 x i64>* %c.addr
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ret void
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}
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attributes #0 = { nounwind "target-features"="+sve" }
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