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[X86] Add CLWB to Tremont CPU. Remove CLDEMOTE, MOVDIRI, MOVDIR64B, and WAITPKG to match gcc.

This commit is contained in:
Craig Topper 2020-06-02 22:21:12 -07:00
parent f51bc4fb60
commit bb1d8bf270
3 changed files with 16 additions and 19 deletions
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5
clang/lib/Basic/Targets/X86.cpp
View File

@ -257,11 +257,8 @@ SkylakeCommon:
break;
case CK_Tremont:
setFeatureEnabledImpl(Features, "cldemote", true);
setFeatureEnabledImpl(Features, "movdiri", true);
setFeatureEnabledImpl(Features, "movdir64b", true);
setFeatureEnabledImpl(Features, "clwb", true);
setFeatureEnabledImpl(Features, "gfni", true);
setFeatureEnabledImpl(Features, "waitpkg", true);
LLVM_FALLTHROUGH;
case CK_GoldmontPlus:
setFeatureEnabledImpl(Features, "ptwrite", true);

18
clang/test/Preprocessor/predefined-arch-macros.c
View File

@ -1802,15 +1802,16 @@
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck %s -check-prefix=CHECK_TRM_M32
// CHECK_TRM_M32: #define __AES__ 1
// CHECK_TRM_M32: #define __CLDEMOTE__ 1
// CHECK_TRM_M32-NOT: #define __CLDEMOTE__ 1
// CHECK_TRM_M32: #define __CLFLUSHOPT__ 1
// CHECK_TRM_M32: #define __CLWB__ 1
// CHECK_TRM_M32: #define __FSGSBASE__ 1
// CHECK_TRM_M32: #define __FXSR__ 1
// CHECK_TRM_M32: #define __GFNI__ 1
// CHECK_TRM_M32: #define __MMX__ 1
// CHECK_TRM_M32: #define __MOVBE__ 1
// CHECK_TRM_M32: #define __MOVDIR64B__ 1
// CHECK_TRM_M32: #define __MOVDIRI__ 1
// CHECK_TRM_M32-NOT: #define __MOVDIR64B__ 1
// CHECK_TRM_M32-NOT: #define __MOVDIRI__ 1
// CHECK_TRM_M32: #define __PCLMUL__ 1
// CHECK_TRM_M32: #define __POPCNT__ 1
// CHECK_TRM_M32: #define __PRFCHW__ 1
@ -1827,7 +1828,7 @@
// CHECK_TRM_M32: #define __SSE_MATH__ 1
// CHECK_TRM_M32: #define __SSE__ 1
// CHECK_TRM_M32: #define __SSSE3__ 1
// CHECK_TRM_M32: #define __WAITPKG__ 1
// CHECK_TRM_M32-NOT: #define __WAITPKG__ 1
// CHECK_TRM_M32: #define __XSAVEC__ 1
// CHECK_TRM_M32: #define __XSAVEOPT__ 1
// CHECK_TRM_M32: #define __XSAVES__ 1
@ -1843,15 +1844,16 @@
// RUN: -target i386-unknown-linux \
// RUN: | FileCheck %s -check-prefix=CHECK_TRM_M64
// CHECK_TRM_M64: #define __AES__ 1
// CHECK_TRM_M64: #define __CLDEMOTE__ 1
// CHECK_TRM_M64-NOT: #define __CLDEMOTE__ 1
// CHECK_TRM_M64: #define __CLFLUSHOPT__ 1
// CHECK_TRM_M64: #define __CLWB__ 1
// CHECK_TRM_M64: #define __FSGSBASE__ 1
// CHECK_TRM_M64: #define __FXSR__ 1
// CHECK_TRM_M64: #define __GFNI__ 1
// CHECK_TRM_M64: #define __MMX__ 1
// CHECK_TRM_M64: #define __MOVBE__ 1
// CHECK_TRM_M64: #define __MOVDIR64B__ 1
// CHECK_TRM_M64: #define __MOVDIRI__ 1
// CHECK_TRM_M64-NOT: #define __MOVDIR64B__ 1
// CHECK_TRM_M64-NOT: #define __MOVDIRI__ 1
// CHECK_TRM_M64: #define __PCLMUL__ 1
// CHECK_TRM_M64: #define __POPCNT__ 1
// CHECK_TRM_M64: #define __PRFCHW__ 1
@ -1867,7 +1869,7 @@
// CHECK_TRM_M64: #define __SSE4_2__ 1
// CHECK_TRM_M64: #define __SSE__ 1
// CHECK_TRM_M64: #define __SSSE3__ 1
// CHECK_TRM_M64: #define __WAITPKG__ 1
// CHECK_TRM_M64-NOT: #define __WAITPKG__ 1
// CHECK_TRM_M64: #define __XSAVEC__ 1
// CHECK_TRM_M64: #define __XSAVEOPT__ 1
// CHECK_TRM_M64: #define __XSAVES__ 1

12
llvm/lib/Target/X86/X86.td
View File

@ -789,15 +789,13 @@ def ProcessorFeatures {
!listconcat(GLPInheritableFeatures, GLPSpecificFeatures);
// Tremont
list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLDEMOTE,
FeatureGFNI,
FeatureMOVDIRI,
FeatureMOVDIR64B,
FeatureWAITPKG];
list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLWB,
FeatureGFNI];
list<SubtargetFeature> TRMSpecificFeatures = [FeatureUseGLMDivSqrtCosts];
list<SubtargetFeature> TRMInheritableFeatures =
!listconcat(GLPInheritableFeatures, TRMAdditionalFeatures);
list<SubtargetFeature> TRMFeatures =
!listconcat(GLPInheritableFeatures, TRMAdditionalFeatures,
TRMSpecificFeatures);
!listconcat(TRMInheritableFeatures, TRMSpecificFeatures);
// Knights Landing
list<SubtargetFeature> KNLFeatures = [FeatureX87,