forked from OSchip/llvm-project
[libunwind] Multiple preprocessor fixes on PowerPC*
* Remove misnamed `PPC64_HAS_VMX` in preference of directly checking `defined(__VSX__)`. libunwind was using "VMX" to mean "VSX". "VMX" is just another name for Altivec, while "VSX" is the vector-scalar extensions first used in POWER7. Exposing a "PPC64_HAS_VMX" define was misleading and incorrect. * Add `defined(__ALTIVEC__)` guards around vector register operations to fix non-altivec CPUS such as the e5500. When compiling for certain Book-E processors such as the e5500, we want to skip vector save/restore, as the Altivec registers are illegal on non-Altivec implementations. * Add `!defined(__NO_FPRS__)` guards around traditional floating-point save/restore. When compiling for powerpcspe, we cannot access floating point registers, as there aren't any. (The SPE on e500v2 is a 64-bit extension of the GPRs, and it doesn't have the normal floating-point registers at all.) This fixes building for powerpcspe, although no actual handling for SPE save/restore is written yet. Reviewed By: MaskRay, #libunwind, compnerd Differential Revision: https://reviews.llvm.org/D91906
This commit is contained in:
Brandon Bergren
Fangrui Song
parent
9194aa8867
commit
bb13411614
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@ -1514,12 +1514,12 @@ inline void Registers_ppc64::setFloatRegister(int regNum, double value) {
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}
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inline bool Registers_ppc64::validVectorRegister(int regNum) const {
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#ifdef PPC64_HAS_VMX
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#if defined(__VSX__)
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if (regNum >= UNW_PPC64_VS0 && regNum <= UNW_PPC64_VS31)
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return true;
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if (regNum >= UNW_PPC64_VS32 && regNum <= UNW_PPC64_VS63)
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return true;
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#else
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#elif defined(__ALTIVEC__)
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if (regNum >= UNW_PPC64_V0 && regNum <= UNW_PPC64_V31)
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return true;
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#endif
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@ -170,7 +170,7 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind15Registers_ppc646jumptoEv)
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PPC64_LR(30)
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PPC64_LR(31)
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#ifdef PPC64_HAS_VMX
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#if defined(__VSX__)
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// restore VS registers
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// (note that this also restores floating point registers and V registers,
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@ -312,6 +312,7 @@ PPC64_CLVS_BOTTOM(n)
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PPC64_LF(30)
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PPC64_LF(31)
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#if defined(__ALTIVEC__)
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// restore vector registers if any are in use
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ld %r5, PPC64_OFFS_VRSAVE(%r3) // test VRsave
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cmpwi %r5, 0
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@ -373,6 +374,7 @@ PPC64_CLV_UNALIGNED_BOTTOM(n)
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PPC64_CLV_UNALIGNEDh(31)
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#endif
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#endif
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Lnovec:
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ld %r0, PPC64_OFFS_CR(%r3)
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@ -431,6 +433,7 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_ppc6jumptoEv)
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lwz %r30,128(%r3)
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lwz %r31,132(%r3)
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#ifndef __NO_FPRS__
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// restore float registers
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lfd %f0, 160(%r3)
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lfd %f1, 168(%r3)
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@ -464,7 +467,9 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_ppc6jumptoEv)
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lfd %f29,392(%r3)
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lfd %f30,400(%r3)
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lfd %f31,408(%r3)
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#endif
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#if defined(__ALTIVEC__)
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// restore vector registers if any are in use
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lwz %r5, 156(%r3) // test VRsave
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cmpwi %r5, 0
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@ -537,6 +542,7 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind13Registers_ppc6jumptoEv)
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LOAD_VECTOR_UNALIGNEDh(29)
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LOAD_VECTOR_UNALIGNEDh(30)
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LOAD_VECTOR_UNALIGNEDh(31)
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#endif
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Lnovec:
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lwz %r0, 136(%r3) // __cr
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@ -384,7 +384,7 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
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mfvrsave %r0
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std %r0, PPC64_OFFS_VRSAVE(%r3)
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#ifdef PPC64_HAS_VMX
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#if defined(__VSX__)
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// save VS registers
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// (note that this also saves floating point registers and V registers,
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// because part of VS is mapped to these registers)
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@ -501,6 +501,7 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
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PPC64_STF(30)
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PPC64_STF(31)
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#if defined(__ALTIVEC__)
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// save vector registers
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// Use 16-bytes below the stack pointer as an
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@ -548,6 +549,7 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
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PPC64_STV_UNALIGNED(30)
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PPC64_STV_UNALIGNED(31)
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#endif
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#endif
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li %r3, 0 // return UNW_ESUCCESS
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@ -608,6 +610,7 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
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mfctr %r0
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stw %r0, 148(%r3)
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#if !defined(__NO_FPRS__)
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// save float registers
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stfd %f0, 160(%r3)
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stfd %f1, 168(%r3)
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@ -641,8 +644,9 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
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stfd %f29,392(%r3)
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stfd %f30,400(%r3)
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stfd %f31,408(%r3)
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#endif
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#if defined(__ALTIVEC__)
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// save vector registers
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subi %r4, %r1, 16
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@ -692,6 +696,7 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
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SAVE_VECTOR_UNALIGNED(%v29, 424+0x1D0)
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SAVE_VECTOR_UNALIGNED(%v30, 424+0x1E0)
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SAVE_VECTOR_UNALIGNED(%v31, 424+0x1F0)
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#endif
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li %r3, 0 // return UNW_ESUCCESS
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blr
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@ -25,9 +25,6 @@
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#define PPC64_OFFS_VRSAVE 304
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#define PPC64_OFFS_FP 312
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#define PPC64_OFFS_V 824
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#ifdef _ARCH_PWR8
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#define PPC64_HAS_VMX
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#endif
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#elif defined(__APPLE__) && defined(__aarch64__)
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#define SEPARATOR %%
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#else
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@ -116,10 +116,6 @@
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#endif
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#endif
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#if defined(__powerpc64__) && defined(_ARCH_PWR8)
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#define PPC64_HAS_VMX
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#endif
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#ifndef _LIBUNWIND_REMEMBER_HEAP_ALLOC
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#if defined(_LIBUNWIND_REMEMBER_STACK_ALLOC) || defined(__APPLE__) || \
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defined(__linux__) || defined(__ANDROID__) || defined(__MINGW32__) || \
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