forked from OSchip/llvm-project
[AVR] Add instruction definitions
Summary: Add the AVR instruction tablegen definitions. Reviewers: stoklund, hfinkel, dsanders, arsenm, vkalintiris Subscribers: dylanmckay, agnat, rjordans, llvm-commits Differential Revision: http://reviews.llvm.org/D15703 llvm-svn: 260363
This commit is contained in:
Dylan McKay
parent
e92e3606dd
commit
bada46c111
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@ -514,9 +514,9 @@ include "AVRRegisterInfo.td"
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// Instruction Descriptions
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//===---------------------------------------------------------------------===//
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//include "AVRInstrInfo.td"
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include "AVRInstrInfo.td"
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//def AVRInstrInfo : InstrInfo;
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def AVRInstrInfo : InstrInfo;
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//===---------------------------------------------------------------------===//
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// Calling Conventions
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@ -554,7 +554,7 @@ include "AVRCallingConv.td"
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//===---------------------------------------------------------------------===//
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def AVR : Target {
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// let InstructionSet = AVRInstrInfo;
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let InstructionSet = AVRInstrInfo;
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// let AssemblyWriters = [AVRAsmWriter];
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//
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// let AssemblyParsers = [AVRAsmParser];
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@ -0,0 +1,577 @@
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//===-- AVRInstrInfo.td - AVR Instruction Formats ----------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// AVR Instruction Format Definitions.
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//
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//===----------------------------------------------------------------------===//
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// A generic AVR instruction.
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class AVRInst<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction
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{
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let Namespace = "AVR";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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}
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/// A 16-bit AVR instruction.
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class AVRInst16<dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst<outs, ins, asmstr, pattern>
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{
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field bits<16> Inst;
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let Size = 2;
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}
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/// a 32-bit AVR instruction.
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class AVRInst32<dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst<outs, ins, asmstr, pattern>
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{
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field bits<32> Inst;
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let Size = 4;
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}
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// A class for pseudo instructions.
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// Psuedo instructions are not real AVR instructions. The DAG stores
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// psuedo instructions which are replaced by real AVR instructions by
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// AVRExpandPseudoInsts.cpp.
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//
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// For example, the ADDW (add wide, as in add 16 bit values) instruction
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// is defined as a pseudo instruction. In AVRExpandPseudoInsts.cpp,
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// the instruction is then replaced by two add instructions - one for each byte.
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst16<outs, ins, asmstr, pattern>
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{
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let Pattern = pattern;
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let isPseudo = 1;
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let isCodeGenOnly = 1;
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}
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//===----------------------------------------------------------------------===//
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// Register / register instruction: <|opcode|ffrd|dddd|rrrr|>
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// opcode = 4 bits.
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// f = secondary opcode = 2 bits
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// d = destination = 5 bits
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// r = source = 5 bits
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// (Accepts all registers)
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//===----------------------------------------------------------------------===//
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class FRdRr<bits<4> opcode, bits<2> f, dag outs, dag ins, string asmstr,
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list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<5> rd;
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bits<5> rr;
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let Inst{15-12} = opcode;
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let Inst{11-10} = f;
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let Inst{9} = rr{4};
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let Inst{8-4} = rd;
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let Inst{3-0} = rr{3-0};
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}
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class FTST<bits<4> opcode, bits<2> f, dag outs, dag ins, string asmstr,
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list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<5> rd;
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let Inst{15-12} = opcode;
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let Inst{11-10} = f;
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let Inst{9} = rd{4};
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let Inst{8-4} = rd;
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let Inst{3-0} = rd{3-0};
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}
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//===----------------------------------------------------------------------===//
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// Instruction of the format `<mnemonic> Z, Rd`
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// <|1001|001r|rrrr|0ttt>
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//===----------------------------------------------------------------------===//
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class FZRd<bits<3> t, dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<5> rd;
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let Inst{15-12} = 0b1001;
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let Inst{11-9} = 0b001;
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let Inst{8} = rd{4};
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let Inst{7-4} = rd{3-0};
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let Inst{3} = 0;
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let Inst{2-0} = t;
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}
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//===----------------------------------------------------------------------===//
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// Register / immediate8 instruction: <|opcode|KKKK|dddd|KKKK|>
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// opcode = 4 bits.
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// K = constant data = 8 bits
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// d = destination = 4 bits
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// (Only accepts r16-r31)
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//===----------------------------------------------------------------------===//
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class FRdK<bits<4> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<4> rd;
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bits<8> k;
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let Inst{15-12} = opcode;
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let Inst{11-8} = k{7-4};
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let Inst{7-4} = rd{3-0};
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let Inst{3-0} = k{3-0};
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let isAsCheapAsAMove = 1;
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}
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//===----------------------------------------------------------------------===//
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// Register instruction: <|opcode|fffd|dddd|ffff|>
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// opcode = 4 bits.
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// f = secondary opcode = 7 bits
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// d = destination = 5 bits
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// (Accepts all registers)
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//===----------------------------------------------------------------------===//
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class FRd<bits<4> opcode, bits<7> f, dag outs, dag ins, string asmstr,
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list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<5> d;
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let Inst{15-12} = opcode;
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let Inst{11-9} = f{6-4};
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let Inst{8-4} = d;
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let Inst{3-0} = f{3-0};
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}
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//===----------------------------------------------------------------------===//
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// [STD/LDD] P+q, Rr special encoding: <|10q0|qqtr|rrrr|pqqq>
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// t = type (1 for STD, 0 for LDD)
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// q = displacement (6 bits)
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// r = register (5 bits)
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// p = pointer register (1 bit) [1 for Y, 0 for Z]
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//===----------------------------------------------------------------------===//
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class FSTDLDD<bit type, dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<7> memri;
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bits<5> reg; // the GP register
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let Inst{15-14} = 0b10;
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let Inst{13} = memri{5};
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let Inst{12} = 0;
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let Inst{11-10} = memri{4-3};
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let Inst{9} = type;
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let Inst{8} = reg{4};
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let Inst{7-4} = reg{3-0};
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let Inst{3} = memri{6};
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let Inst{2-0} = memri{2-0};
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}
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//===---------------------------------------------------------------------===//
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// An ST/LD instruction.
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// <|100i|00tr|rrrr|ppaa|>
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// t = type (1 for store, 0 for load)
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// a = regular/postinc/predec (reg = 0b00, postinc = 0b01, predec = 0b10)
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// p = pointer register
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// r = src/dst register
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//
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// Note that the bit labelled 'i' above does not follow a simple pattern,
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// so there exists a post encoder method to set it manually.
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//===---------------------------------------------------------------------===//
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class FSTLD<bit type, bits<2> mode, dag outs, dag ins,
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string asmstr, list<dag> pattern>
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: AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<2> ptrreg;
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bits<5> reg;
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let Inst{15-13} = 0b100;
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// This bit varies depending on the arguments and the mode.
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// We have a post encoder method to set this bit manually.
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let Inst{12} = 0;
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let Inst{11-10} = 0b00;
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let Inst{9} = type;
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let Inst{8} = reg{4};
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let Inst{7-4} = reg{3-0};
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let Inst{3-2} = ptrreg{1-0};
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let Inst{1-0} = mode{1-0};
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let PostEncoderMethod = "loadStorePostEncoder";
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}
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//===---------------------------------------------------------------------===//
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// Special format for the LPM/ELPM instructions
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// [E]LPM Rd, Z[+]
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// <|1001|000d|dddd|01ep>
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// d = destination register
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// e = is elpm
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// p = is postincrement
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//===---------------------------------------------------------------------===//
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class FLPMX<bit e, bit p, dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<5> reg;
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let Inst{15-12} = 0b1001;
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let Inst{11-9} = 0b000;
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let Inst{8} = reg{4};
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let Inst{7-4} = reg{3-0};
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let Inst{3-2} = 0b01;
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let Inst{1} = e;
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let Inst{0} = p;
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}
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//===----------------------------------------------------------------------===//
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// MOVWRdRr special encoding: <|0000|0001|dddd|rrrr|>
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// d = destination = 4 bits
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// r = source = 4 bits
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// (Only accepts even registers)
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//===----------------------------------------------------------------------===//
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class FMOVWRdRr<dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<5> d;
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bits<5> r;
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let Inst{15-8} = 0b00000001;
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let Inst{7-4} = d{4-1};
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let Inst{3-0} = r{4-1};
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}
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//===----------------------------------------------------------------------===//
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// MULSrr special encoding: <|0000|0010|dddd|rrrr|>
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// d = multiplicand = 4 bits
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// r = multiplier = 4 bits
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// (Only accepts r16-r31)
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//===----------------------------------------------------------------------===//
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class FMUL2RdRr<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<5> rd; // accept 5 bits but only encode the lower 4
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bits<5> rr; // accept 5 bits but only encode the lower 4
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let Inst{15-9} = 0b0000001;
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let Inst{8} = f;
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let Inst{7-4} = rd{3-0};
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let Inst{3-0} = rr{3-0};
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}
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// Special encoding for the FMUL family of instructions.
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//
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// <0000|0011|fddd|frrr|>
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//
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// ff = 0b01 for FMUL
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// 0b10 for FMULS
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// 0b11 for FMULSU
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//
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// ddd = destination register
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// rrr = source register
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class FFMULRdRr<bits<2> f, dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<3> rd;
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bits<3> rr;
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let Inst{15-8} = 0b00000011;
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let Inst{7} = f{1};
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let Inst{6-4} = rd;
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let Inst{3} = f{0};
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let Inst{2-0} = rr;
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}
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//===----------------------------------------------------------------------===//
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// Arithmetic word instructions (ADIW / SBIW): <|1001|011f|kkdd|kkkk|>
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// f = secondary opcode = 1 bit
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// k = constant data = 6 bits
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// d = destination = 4 bits
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// (Only accepts r25:24 r27:26 r29:28 r31:30)
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//===----------------------------------------------------------------------===//
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class FWRdK<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<5> dst; // accept 5 bits but only encode bits 1 and 2
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bits<6> k;
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let Inst{15-9} = 0b1001011;
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let Inst{8} = f;
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let Inst{7-6} = k{5-4};
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let Inst{5-4} = dst{2-1};
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let Inst{3-0} = k{3-0};
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}
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//===----------------------------------------------------------------------===//
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// In I/O instruction: <|1011|0AAd|dddd|AAAA|>
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// A = I/O location address = 6 bits
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// d = destination = 5 bits
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// (Accepts all registers)
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//===----------------------------------------------------------------------===//
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class FIORdA<dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<5> d;
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bits<6> A;
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let Inst{15-11} = 0b10110;
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let Inst{10-9} = A{5-4};
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let Inst{8-4} = d;
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let Inst{3-0} = A{3-0};
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}
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//===----------------------------------------------------------------------===//
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// Out I/O instruction: <|1011|1AAr|rrrr|AAAA|>
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// A = I/O location address = 6 bits
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// d = destination = 5 bits
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// (Accepts all registers)
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//===----------------------------------------------------------------------===//
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class FIOARr<dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<6> A;
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bits<5> r;
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let Inst{15-11} = 0b10111;
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let Inst{10-9} = A{5-4};
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let Inst{8-4} = r;
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let Inst{3-0} = A{3-0};
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}
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//===----------------------------------------------------------------------===//
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// I/O bit instruction.
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// <|1001|10tt|AAAA|Abbb>
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// t = type (1 for SBI, 0 for CBI)
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// A = I/O location address (5 bits)
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// b = bit number
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//===----------------------------------------------------------------------===//
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class FIOBIT<bits<2> t, dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<5> A;
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bits<3> b;
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let Inst{15-12} = 0b1001;
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let Inst{11-10} = 0b10;
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let Inst{9-8} = t;
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let Inst{7-4} = A{4-1};
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let Inst{3} = A{0};
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let Inst{2-0} = b{2-0};
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}
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//===----------------------------------------------------------------------===//
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// BST/BLD instruction.
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// <|1111|1ttd|dddd|0bbb>
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// t = type (1 for BST, 0 for BLD)
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// d = destination register
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// b = bit
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//===----------------------------------------------------------------------===//
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class FRdB<bits<2> t, dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<5> rd;
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bits<3> b;
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let Inst{15-12} = 0b1111;
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let Inst{11} = 0b1;
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let Inst{10-9} = t;
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let Inst{8} = rd{4};
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let Inst{7-4} = rd{3-0};
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let Inst{3} = 0;
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let Inst{2-0} = b;
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}
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// Special encoding for the `DES K` instruction.
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//
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// <|1001|0100|KKKK|1011>
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//
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// KKKK = 4 bit immediate
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class FDES<dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<4> k;
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let Inst{15-12} = 0b1001;
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let Inst{11-8} = 0b0100;
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let Inst{7-4} = k;
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let Inst{3-0} = 0b1011;
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}
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//===----------------------------------------------------------------------===//
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// Conditional Branching instructions: <|1111|0fkk|kkkk|ksss|>
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// f = secondary opcode = 1 bit
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// k = constant address = 7 bits
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// s = bit in status register = 3 bits
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//===----------------------------------------------------------------------===//
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class FBRsk<bit f, bits<3> s, dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst16<outs, ins, asmstr, pattern>
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{
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bits<7> k;
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let Inst{15-11} = 0b11110;
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let Inst{10} = f;
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let Inst{9-3} = k;
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let Inst{2-0} = s;
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}
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//===----------------------------------------------------------------------===//
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// Special, opcode only instructions: <|opcode|>
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//===----------------------------------------------------------------------===//
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class F16<bits<16> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
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: AVRInst16<outs, ins, asmstr, pattern>
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{
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let Inst = opcode;
|
||||
}
|
||||
|
||||
class F32<bits<32> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: AVRInst32<outs, ins, asmstr, pattern>
|
||||
{
|
||||
let Inst = opcode;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Branching instructions with immediate12: <|110f|kkkk|kkkk|kkkk|>
|
||||
// f = secondary opcode = 1 bit
|
||||
// k = constant address = 12 bits
|
||||
//===----------------------------------------------------------------------===//
|
||||
class FBRk<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: AVRInst16<outs, ins, asmstr, pattern>
|
||||
{
|
||||
bits<12> k;
|
||||
|
||||
let Inst{15-13} = 0b110;
|
||||
let Inst{12} = f;
|
||||
let Inst{11-0} = k;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// 32 bits branching instructions: <|1001|010k|kkkk|fffk|kkkk|kkkk|kkkk|kkkk|>
|
||||
// f = secondary opcode = 3 bits
|
||||
// k = constant address = 22 bits
|
||||
//===----------------------------------------------------------------------===//
|
||||
class F32BRk<bits<3> f, dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: AVRInst32<outs, ins, asmstr, pattern>
|
||||
{
|
||||
bits<22> k;
|
||||
|
||||
let Inst{31-25} = 0b1001010;
|
||||
let Inst{24-20} = k{21-17};
|
||||
let Inst{19-17} = f;
|
||||
let Inst{16-0} = k{16-0};
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// 32 bits direct mem instructions: <|1001|00fd|dddd|0000|kkkk|kkkk|kkkk|kkkk|>
|
||||
// f = secondary opcode = 1 bit
|
||||
// d = destination = 5 bits
|
||||
// k = constant address = 16 bits
|
||||
// (Accepts all registers)
|
||||
//===----------------------------------------------------------------------===//
|
||||
class F32DM<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: AVRInst32<outs, ins, asmstr, pattern>
|
||||
{
|
||||
bits<5> rd;
|
||||
bits<16> k;
|
||||
|
||||
let Inst{31-28} = 0b1001;
|
||||
|
||||
let Inst{27-26} = 0b00;
|
||||
let Inst{25} = f;
|
||||
let Inst{24} = rd{4};
|
||||
|
||||
let Inst{23-20} = rd{3-0};
|
||||
|
||||
let Inst{19-16} = 0b0000;
|
||||
|
||||
let Inst{15-0} = k;
|
||||
}
|
||||
|
||||
// <|1001|0100|bfff|1000>
|
||||
class FS<bit b, dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: AVRInst16<outs, ins, asmstr, pattern>
|
||||
{
|
||||
bits<3> s;
|
||||
|
||||
let Inst{15-12} = 0b1001;
|
||||
|
||||
let Inst{11-8} = 0b0100;
|
||||
|
||||
let Inst{7} = b;
|
||||
let Inst{6-4} = s;
|
||||
|
||||
let Inst{3-0} = 0b1000;
|
||||
}
|
||||
|
||||
// Set/clr bit in status flag instructions/
|
||||
// <BRBS|BRBC> s, k
|
||||
// ---------------------
|
||||
// <|1111|0fkk|kkkk|ksss>
|
||||
class FSK<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: AVRInst16<outs, ins, asmstr, pattern>
|
||||
{
|
||||
bits<7> k;
|
||||
bits<3> s;
|
||||
|
||||
let Inst{15-12} = 0b1111;
|
||||
|
||||
let Inst{11} = 0;
|
||||
let Inst{10} = f;
|
||||
let Inst{9-8} = k{6-5};
|
||||
|
||||
let Inst{7-4} = k{4-1};
|
||||
|
||||
let Inst{3} = k{0};
|
||||
let Inst{2-0} = s;
|
||||
}
|
||||
|
||||
class ExtensionPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: Pseudo<outs, ins, asmstr, pattern>
|
||||
{
|
||||
let Defs = [SREG];
|
||||
}
|
||||
|
||||
class StorePseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: Pseudo<outs, ins, asmstr, pattern>
|
||||
{
|
||||
let Defs = [SP];
|
||||
}
|
||||
|
||||
class SelectPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: Pseudo<outs, ins, asmstr, pattern>
|
||||
{
|
||||
let usesCustomInserter = 1;
|
||||
|
||||
let Uses = [SREG];
|
||||
}
|
||||
|
||||
class ShiftPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: Pseudo<outs, ins, asmstr, pattern>
|
||||
{
|
||||
let usesCustomInserter = 1;
|
||||
|
||||
let Defs = [SREG];
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,6 +1,7 @@
|
|||
set(LLVM_TARGET_DEFINITIONS AVR.td)
|
||||
|
||||
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
|
||||
tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
|
||||
tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
|
||||
add_public_tablegen_target(AVRCommonTableGen)
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,7 @@
|
|||
# Write an XFAIL test for this `FIXME` in `AVRInstrInfo.td`
|
||||
|
||||
```
|
||||
// :FIXME: DAGCombiner produces an shl node after legalization from these seq:
|
||||
// BR_JT -> (mul x, 2) -> (shl x, 1)
|
||||
```
|
||||
|
||||
Loading…
Reference in New Issue