forked from OSchip/llvm-project
[AMDGPU] Regenerate weird stores tests.
Makes an upcoming SimplifyDemandedBits optimization much easier to understand. llvm-svn: 347326
This commit is contained in:
Simon Pilgrim
parent
c21fba1bab
commit
bac49ac455
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@ -1,64 +1,236 @@
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,HAWAII %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,FIJI %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
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; GCN-LABEL: {{^}}local_store_i56:
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; CIVI-DAG: ds_write_b8 v0, v{{[0-9]+}} offset:6
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; CIVI-DAG: ds_write_b16 v0, v{{[0-9]+}} offset:4
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; CIVI-DAG: ds_write_b32 v0, v{{[0-9]+$}}
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; GFX9-DAG: ds_write_b8_d16_hi v0, v{{[0-9]+}} offset:6
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; GFX9-DAG: ds_write_b16 v0, v{{[0-9]+}} offset:4
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; GFX9-DAG: ds_write_b32 v0, v{{[0-9]+$}}
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define void @local_store_i56(i56 addrspace(3)* %ptr, i56 %arg) #0 {
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; CIVI-LABEL: local_store_i56:
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; CIVI: ; %bb.0:
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; CIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CIVI-NEXT: s_mov_b32 m0, -1
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; CIVI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
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; CIVI-NEXT: ds_write_b16 v0, v2 offset:4
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; CIVI-NEXT: ds_write_b32 v0, v1
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; CIVI-NEXT: ds_write_b8 v0, v3 offset:6
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; CIVI-NEXT: s_waitcnt lgkmcnt(0)
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; CIVI-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-LABEL: local_store_i56:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: ds_write_b8_d16_hi v0, v2 offset:6
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; GFX9-NEXT: ds_write_b16 v0, v2 offset:4
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; GFX9-NEXT: ds_write_b32 v0, v1
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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store i56 %arg, i56 addrspace(3)* %ptr, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_store_i55:
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; CIVI-DAG: ds_write_b8 v{{[0-9]+}}, v{{[0-9]+}} offset:6
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; CIVI-DAG: ds_write_b16 v{{[0-9]+}}, v{{[0-9]+}} offset:4
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; CIVI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+$}}
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; GFX9-DAG: ds_write_b8_d16_hi v0, v{{[0-9]+}} offset:6
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; GFX9-DAG: ds_write_b16 v0, v{{[0-9]+}} offset:4
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; GFX9-DAG: ds_write_b32 v0, v{{[0-9]+$}}
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define amdgpu_kernel void @local_store_i55(i55 addrspace(3)* %ptr, i55 %arg) #0 {
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; HAWAII-LABEL: local_store_i55:
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; HAWAII: ; %bb.0:
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; HAWAII-NEXT: s_add_u32 s0, s4, 14
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; HAWAII-NEXT: s_addc_u32 s1, s5, 0
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; HAWAII-NEXT: v_mov_b32_e32 v0, s0
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; HAWAII-NEXT: v_mov_b32_e32 v1, s1
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; HAWAII-NEXT: flat_load_ubyte v0, v[0:1]
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; HAWAII-NEXT: s_load_dword s0, s[4:5], 0x0
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; HAWAII-NEXT: s_load_dword s1, s[4:5], 0x2
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; HAWAII-NEXT: s_load_dword s2, s[4:5], 0x3
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; HAWAII-NEXT: s_mov_b32 m0, -1
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; HAWAII-NEXT: s_waitcnt lgkmcnt(0)
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; HAWAII-NEXT: v_mov_b32_e32 v1, s0
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; HAWAII-NEXT: v_mov_b32_e32 v3, s1
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; HAWAII-NEXT: v_mov_b32_e32 v2, s2
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; HAWAII-NEXT: ds_write_b16 v1, v2 offset:4
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; HAWAII-NEXT: s_waitcnt vmcnt(0)
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; HAWAII-NEXT: v_and_b32_e32 v0, 0x7f, v0
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; HAWAII-NEXT: ds_write_b8 v1, v0 offset:6
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; HAWAII-NEXT: ds_write_b32 v1, v3
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; HAWAII-NEXT: s_endpgm
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;
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; FIJI-LABEL: local_store_i55:
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; FIJI: ; %bb.0:
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; FIJI-NEXT: s_add_u32 s0, s4, 14
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; FIJI-NEXT: s_addc_u32 s1, s5, 0
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; FIJI-NEXT: v_mov_b32_e32 v0, s0
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; FIJI-NEXT: v_mov_b32_e32 v1, s1
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; FIJI-NEXT: flat_load_ubyte v0, v[0:1]
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; FIJI-NEXT: s_load_dword s0, s[4:5], 0x0
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; FIJI-NEXT: s_load_dword s1, s[4:5], 0x8
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; FIJI-NEXT: s_load_dword s2, s[4:5], 0xc
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; FIJI-NEXT: s_mov_b32 m0, -1
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; FIJI-NEXT: s_waitcnt lgkmcnt(0)
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; FIJI-NEXT: v_mov_b32_e32 v1, s0
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; FIJI-NEXT: v_mov_b32_e32 v3, s1
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; FIJI-NEXT: v_mov_b32_e32 v2, s2
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; FIJI-NEXT: ds_write_b16 v1, v2 offset:4
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; FIJI-NEXT: s_waitcnt vmcnt(0)
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; FIJI-NEXT: v_and_b32_e32 v0, 0x7f, v0
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; FIJI-NEXT: ds_write_b8 v1, v0 offset:6
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; FIJI-NEXT: ds_write_b32 v1, v3
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; FIJI-NEXT: s_endpgm
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;
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; GFX9-LABEL: local_store_i55:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: v_mov_b32_e32 v0, s4
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; GFX9-NEXT: v_mov_b32_e32 v1, s5
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; GFX9-NEXT: v_mov_b32_e32 v2, 0
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; GFX9-NEXT: global_load_ubyte_d16_hi v2, v[0:1], off offset:14
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; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0
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; GFX9-NEXT: s_load_dword s1, s[4:5], 0x8
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; GFX9-NEXT: s_load_dword s2, s[4:5], 0xc
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, s0
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; GFX9-NEXT: v_mov_b32_e32 v3, s1
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; GFX9-NEXT: v_mov_b32_e32 v1, s2
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; GFX9-NEXT: ds_write_b16 v0, v1 offset:4
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_and_b32_e32 v1, 0x7f0000, v2
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; GFX9-NEXT: ds_write_b8_d16_hi v0, v1 offset:6
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; GFX9-NEXT: ds_write_b32 v0, v3
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; GFX9-NEXT: s_endpgm
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store i55 %arg, i55 addrspace(3)* %ptr, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_store_i48:
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; GCN-DAG: ds_write_b16 v0, v{{[0-9]+}} offset:4
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; GCN-DAG: ds_write_b32 v0, v{{[0-9]+$}}
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define amdgpu_kernel void @local_store_i48(i48 addrspace(3)* %ptr, i48 %arg) #0 {
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; HAWAII-LABEL: local_store_i48:
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; HAWAII: ; %bb.0:
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; HAWAII-NEXT: s_load_dword s0, s[4:5], 0x0
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; HAWAII-NEXT: s_load_dword s1, s[4:5], 0x2
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; HAWAII-NEXT: s_load_dword s2, s[4:5], 0x3
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; HAWAII-NEXT: s_mov_b32 m0, -1
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; HAWAII-NEXT: s_waitcnt lgkmcnt(0)
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; HAWAII-NEXT: v_mov_b32_e32 v0, s0
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; HAWAII-NEXT: v_mov_b32_e32 v1, s1
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; HAWAII-NEXT: v_mov_b32_e32 v2, s2
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; HAWAII-NEXT: ds_write_b16 v0, v2 offset:4
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; HAWAII-NEXT: ds_write_b32 v0, v1
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; HAWAII-NEXT: s_endpgm
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;
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; FIJI-LABEL: local_store_i48:
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; FIJI: ; %bb.0:
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; FIJI-NEXT: s_load_dword s0, s[4:5], 0x0
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; FIJI-NEXT: s_load_dword s1, s[4:5], 0x8
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; FIJI-NEXT: s_load_dword s2, s[4:5], 0xc
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; FIJI-NEXT: s_mov_b32 m0, -1
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; FIJI-NEXT: s_waitcnt lgkmcnt(0)
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; FIJI-NEXT: v_mov_b32_e32 v0, s0
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; FIJI-NEXT: v_mov_b32_e32 v1, s1
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; FIJI-NEXT: v_mov_b32_e32 v2, s2
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; FIJI-NEXT: ds_write_b16 v0, v2 offset:4
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; FIJI-NEXT: ds_write_b32 v0, v1
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; FIJI-NEXT: s_endpgm
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;
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; GFX9-LABEL: local_store_i48:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0
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; GFX9-NEXT: s_load_dword s1, s[4:5], 0x8
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; GFX9-NEXT: s_load_dword s2, s[4:5], 0xc
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, s0
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; GFX9-NEXT: v_mov_b32_e32 v1, s1
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; GFX9-NEXT: v_mov_b32_e32 v2, s2
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; GFX9-NEXT: ds_write_b16 v0, v2 offset:4
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; GFX9-NEXT: ds_write_b32 v0, v1
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; GFX9-NEXT: s_endpgm
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store i48 %arg, i48 addrspace(3)* %ptr, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_store_i65:
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; GCN-DAG: ds_write_b8 v{{[0-9]+}}, v{{[0-9]+}} offset:8
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; GCN-DAG: ds_write_b64
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define amdgpu_kernel void @local_store_i65(i65 addrspace(3)* %ptr, i65 %arg) #0 {
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; HAWAII-LABEL: local_store_i65:
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; HAWAII: ; %bb.0:
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; HAWAII-NEXT: s_load_dword s2, s[4:5], 0x0
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; HAWAII-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2
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; HAWAII-NEXT: s_load_dword s3, s[4:5], 0x4
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; HAWAII-NEXT: s_mov_b32 m0, -1
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; HAWAII-NEXT: s_waitcnt lgkmcnt(0)
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; HAWAII-NEXT: v_mov_b32_e32 v2, s2
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; HAWAII-NEXT: v_mov_b32_e32 v0, s0
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; HAWAII-NEXT: v_mov_b32_e32 v1, s1
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; HAWAII-NEXT: s_and_b32 s0, s3, 1
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; HAWAII-NEXT: v_mov_b32_e32 v3, s0
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; HAWAII-NEXT: ds_write_b8 v2, v3 offset:8
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; HAWAII-NEXT: ds_write_b64 v2, v[0:1]
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; HAWAII-NEXT: s_endpgm
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;
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; FIJI-LABEL: local_store_i65:
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; FIJI: ; %bb.0:
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; FIJI-NEXT: s_load_dword s2, s[4:5], 0x0
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; FIJI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
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; FIJI-NEXT: s_load_dword s3, s[4:5], 0x10
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; FIJI-NEXT: s_mov_b32 m0, -1
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; FIJI-NEXT: s_waitcnt lgkmcnt(0)
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; FIJI-NEXT: v_mov_b32_e32 v2, s2
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; FIJI-NEXT: v_mov_b32_e32 v0, s0
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; FIJI-NEXT: v_mov_b32_e32 v1, s1
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; FIJI-NEXT: s_and_b32 s0, s3, 1
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; FIJI-NEXT: v_mov_b32_e32 v3, s0
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; FIJI-NEXT: ds_write_b8 v2, v3 offset:8
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; FIJI-NEXT: ds_write_b64 v2, v[0:1]
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; FIJI-NEXT: s_endpgm
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;
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; GFX9-LABEL: local_store_i65:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dword s2, s[4:5], 0x0
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
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; GFX9-NEXT: s_load_dword s3, s[4:5], 0x10
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v2, s2
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; GFX9-NEXT: v_mov_b32_e32 v0, s0
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; GFX9-NEXT: v_mov_b32_e32 v1, s1
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; GFX9-NEXT: s_and_b32 s0, s3, 1
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; GFX9-NEXT: v_mov_b32_e32 v3, s0
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; GFX9-NEXT: ds_write_b8 v2, v3 offset:8
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; GFX9-NEXT: ds_write_b64 v2, v[0:1]
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; GFX9-NEXT: s_endpgm
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store i65 %arg, i65 addrspace(3)* %ptr, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_store_i13:
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; GCN: v_and_b32_e32 [[TRUNC:v[0-9]+]], 0x1fff, v1
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; GCN: ds_write_b16 v0, [[TRUNC]]
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define void @local_store_i13(i13 addrspace(3)* %ptr, i13 %arg) #0 {
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; CIVI-LABEL: local_store_i13:
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; CIVI: ; %bb.0:
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; CIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CIVI-NEXT: v_and_b32_e32 v1, 0x1fff, v1
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; CIVI-NEXT: s_mov_b32 m0, -1
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; CIVI-NEXT: ds_write_b16 v0, v1
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; CIVI-NEXT: s_waitcnt lgkmcnt(0)
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; CIVI-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-LABEL: local_store_i13:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_and_b32_e32 v1, 0x1fff, v1
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; GFX9-NEXT: ds_write_b16 v0, v1
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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store i13 %arg, i13 addrspace(3)* %ptr, align 8
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ret void
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}
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; GCN-LABEL: {{^}}local_store_i17:
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; GCN: ds_write_b16 v0
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; CIVI: ds_write_b8 v0, v{{[0-9]+}} offset:2
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; GFX9: ds_write_b8_d16_hi v0, v{{[0-9]+}} offset:2
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define void @local_store_i17(i17 addrspace(3)* %ptr, i17 %arg) #0 {
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; CIVI-LABEL: local_store_i17:
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; CIVI: ; %bb.0:
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; CIVI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CIVI-NEXT: v_bfe_u32 v2, v1, 16, 1
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; CIVI-NEXT: s_mov_b32 m0, -1
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; CIVI-NEXT: ds_write_b16 v0, v1
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; CIVI-NEXT: ds_write_b8 v0, v2 offset:2
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; CIVI-NEXT: s_waitcnt lgkmcnt(0)
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; CIVI-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-LABEL: local_store_i17:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: ds_write_b16 v0, v1
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; GFX9-NEXT: v_and_b32_e32 v1, 0x1ffff, v1
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; GFX9-NEXT: ds_write_b8_d16_hi v0, v1 offset:2
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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store i17 %arg, i17 addrspace(3)* %ptr, align 8
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ret void
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}
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