maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[NFC][MC] TargetRegisterInfo::getSubReg is a MCRegister. 

Typing the API appropriately.

Differential Revision: https://reviews.llvm.org/D92341
This commit is contained in:
Mircea Trofin 2020-11-19 07:43:56 -08:00
parent 640567d464
commit bab72dd5d5
12 changed files with 40 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
View File

@ -1030,7 +1030,7 @@ public:
/// Returns the physical register number of sub-register "Index"
/// for physical register RegNo. Return zero if the sub-register does not
/// exist.
inline Register getSubReg(MCRegister Reg, unsigned Idx) const {
inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const {
return static_cast<const MCRegisterInfo *>(this)->getSubReg(Reg, Idx);
}
};

2
llvm/lib/CodeGen/CalcSpillWeights.cpp
View File

@ -64,7 +64,7 @@ static Register copyHint(const MachineInstr *MI, unsigned Reg,
return Sub == HSub ? HReg : Register();
const TargetRegisterClass *rc = MRI.getRegClass(Reg);
Register CopiedPReg = (HSub ? TRI.getSubReg(HReg, HSub) : HReg);
MCRegister CopiedPReg = HSub ? TRI.getSubReg(HReg, HSub) : HReg.asMCReg();
if (rc->contains(CopiedPReg))
return CopiedPReg;

2
llvm/lib/CodeGen/RegAllocFast.cpp
View File

@ -950,7 +950,7 @@ void RegAllocFast::setPhysReg(MachineInstr &MI, MachineOperand &MO,
}
// Handle subregister index.
MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : Register());
MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : MCRegister());
MO.setIsRenamable(true);
// Note: We leave the subreg number around a little longer in case of defs.
// This is so that the register freeing logic in allocateInstruction can still

6
llvm/lib/CodeGen/RegisterCoalescer.cpp
View File

@ -538,8 +538,8 @@ bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
}
// Now check that Dst matches DstReg.
if (Register::isPhysicalRegister(DstReg)) {
if (!Register::isPhysicalRegister(Dst))
if (DstReg.isPhysical()) {
if (!Dst.isPhysical())
return false;
assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.");
// DstSub could be set for a physreg from INSERT_SUBREG.
@ -549,7 +549,7 @@ bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
if (!SrcSub)
return DstReg == Dst;
// This is a partial register copy. Check that the parts match.
return TRI.getSubReg(DstReg, SrcSub) == Dst;
return Register(TRI.getSubReg(DstReg, SrcSub)) == Dst;
} else {
// DstReg is virtual.
if (DstReg != Dst)

40
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
View File

@ -840,9 +840,10 @@ void SIRegisterInfo::buildSpillLoadStore(MachineBasicBlock::iterator MI,
// FIXME: Flat scratch does not have to be limited to a dword per store.
for (unsigned i = 0, e = NumSubRegs; i != e; ++i, Offset += EltSize) {
Register SubReg = NumSubRegs == 1
? Register(ValueReg)
: getSubReg(ValueReg, getSubRegFromChannel(i));
Register SubReg =
NumSubRegs == 1
? ValueReg
: Register(getSubReg(ValueReg, getSubRegFromChannel(i)));
unsigned SOffsetRegState = 0;
unsigned SrcDstRegState = getDefRegState(!IsStore);
@ -968,9 +969,10 @@ void SIRegisterInfo::buildSGPRSpillLoadStore(MachineBasicBlock::iterator MI,
// Backup EXEC
if (OnlyExecLo) {
SavedExecReg = NumSubRegs == 1
? SuperReg
: getSubReg(SuperReg, SplitParts[FirstPart + ExecLane]);
SavedExecReg =
NumSubRegs == 1
? SuperReg
: Register(getSubReg(SuperReg, SplitParts[FirstPart + ExecLane]));
} else {
// If src/dst is an odd size it is possible subreg0 is not aligned.
for (; ExecLane < (NumSubRegs - 1); ++ExecLane) {
@ -1037,9 +1039,9 @@ void SIRegisterInfo::buildSGPRSpillLoadStore(MachineBasicBlock::iterator MI,
.addImm(ExecLane + 1);
}
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32),
NumSubRegs == 1
? SavedExecReg
: getSubReg(SuperReg, SplitParts[FirstPart + ExecLane]))
NumSubRegs == 1 ? SavedExecReg
: Register(getSubReg(
SuperReg, SplitParts[FirstPart + ExecLane])))
.addReg(VGPR, RegState::Kill)
.addImm(ExecLane);
}
@ -1081,8 +1083,9 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
if (SpillToVGPR) {
for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
Register SubReg =
NumSubRegs == 1 ? SuperReg : getSubReg(SuperReg, SplitParts[i]);
Register SubReg = NumSubRegs == 1
? SuperReg
: Register(getSubReg(SuperReg, SplitParts[i]));
SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i];
bool UseKill = IsKill && i == NumSubRegs - 1;
@ -1135,8 +1138,9 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
for (unsigned i = Offset * PerVGPR,
e = std::min((Offset + 1) * PerVGPR, NumSubRegs);
i < e; ++i) {
Register SubReg =
NumSubRegs == 1 ? SuperReg : getSubReg(SuperReg, SplitParts[i]);
Register SubReg = NumSubRegs == 1
? SuperReg
: Register(getSubReg(SuperReg, SplitParts[i]));
MachineInstrBuilder WriteLane =
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_WRITELANE_B32), TmpVGPR)
@ -1199,8 +1203,9 @@ bool SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI,
if (SpillToVGPR) {
for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
Register SubReg =
NumSubRegs == 1 ? SuperReg : getSubReg(SuperReg, SplitParts[i]);
Register SubReg = NumSubRegs == 1
? SuperReg
: Register(getSubReg(SuperReg, SplitParts[i]));
SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i];
auto MIB = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg)
@ -1226,8 +1231,9 @@ bool SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI,
for (unsigned i = Offset * PerVGPR,
e = std::min((Offset + 1) * PerVGPR, NumSubRegs);
i < e; ++i) {
Register SubReg =
NumSubRegs == 1 ? SuperReg : getSubReg(SuperReg, SplitParts[i]);
Register SubReg = NumSubRegs == 1
? SuperReg
: Register(getSubReg(SuperReg, SplitParts[i]));
bool LastSubReg = (i + 1 == e);
auto MIB =

2
llvm/lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -285,7 +285,7 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
return false;
case 'y': // Print a VFP single precision register as indexed double.
if (MI->getOperand(OpNum).isReg()) {
Register Reg = MI->getOperand(OpNum).getReg();
MCRegister Reg = MI->getOperand(OpNum).getReg().asMCReg();
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
// Find the 'd' register that has this 's' register as a sub-register,
// and determine the lane number.

7
llvm/lib/Target/Hexagon/BitTracker.cpp
View File

@ -340,8 +340,8 @@ uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const {
return TRI.getRegSizeInBits(VC);
}
assert(RR.Reg.isPhysical());
Register PhysR =
(RR.Sub == 0) ? Register(RR.Reg) : TRI.getSubReg(RR.Reg, RR.Sub);
MCRegister PhysR =
(RR.Sub == 0) ? RR.Reg.asMCReg() : TRI.getSubReg(RR.Reg, RR.Sub);
return getPhysRegBitWidth(PhysR);
}
@ -711,8 +711,7 @@ BT::BitMask BT::MachineEvaluator::mask(Register Reg, unsigned Sub) const {
return BitMask(0, W-1);
}
uint16_t BT::MachineEvaluator::getPhysRegBitWidth(Register Reg) const {
assert(Reg.isPhysical());
uint16_t BT::MachineEvaluator::getPhysRegBitWidth(MCRegister Reg) const {
const TargetRegisterClass &PC = *TRI.getMinimalPhysRegClass(Reg);
return TRI.getRegSizeInBits(PC);
}

2
llvm/lib/Target/Hexagon/BitTracker.h
View File

@ -485,7 +485,7 @@ struct BitTracker::MachineEvaluator {
llvm_unreachable("Unimplemented composeWithSubRegIndex");
}
// Return the size in bits of the physical register Reg.
virtual uint16_t getPhysRegBitWidth(Register Reg) const;
virtual uint16_t getPhysRegBitWidth(MCRegister Reg) const;
const TargetRegisterInfo &TRI;
MachineRegisterInfo &MRI;

4
llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
View File

@ -110,9 +110,7 @@ BT::BitMask HexagonEvaluator::mask(Register Reg, unsigned Sub) const {
llvm_unreachable("Unexpected register/subregister");
}
uint16_t HexagonEvaluator::getPhysRegBitWidth(Register Reg) const {
assert(Reg.isPhysical());
uint16_t HexagonEvaluator::getPhysRegBitWidth(MCRegister Reg) const {
using namespace Hexagon;
const auto &HST = MF.getSubtarget<HexagonSubtarget>();
if (HST.useHVXOps()) {

2
llvm/lib/Target/Hexagon/HexagonBitTracker.h
View File

@ -38,7 +38,7 @@ struct HexagonEvaluator : public BitTracker::MachineEvaluator {
BitTracker::BitMask mask(Register Reg, unsigned Sub) const override;
uint16_t getPhysRegBitWidth(Register Reg) const override;
uint16_t getPhysRegBitWidth(MCRegister Reg) const override;
const TargetRegisterClass &composeWithSubRegIndex(
const TargetRegisterClass &RC, unsigned Idx) const override;

5
llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
View File

@ -582,17 +582,16 @@ unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
using namespace Hexagon;
if (SO.isReg()) {
Register PhysR;
MCRegister PhysR;
RegisterRef RS = SO;
if (RS.Reg.isVirtual()) {
const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
assert(VC->begin() != VC->end() && "Empty register class");
PhysR = *VC->begin();
} else {
assert(Register::isPhysicalRegister(RS.Reg));
PhysR = RS.Reg;
}
Register PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
MCRegister PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS);
switch (TRI->getRegSizeInBits(*RC)) {
case 32:

4
llvm/lib/Target/Mips/MipsExpandPseudo.cpp
View File

@ -733,10 +733,10 @@ bool MipsExpandPseudo::expandAtomicBinOp(MachineBasicBlock &BB,
assert(I->getNumOperands() == 5 &&
"Atomics min|max|umin|umax use an additional register");
Register Scratch2 = I->getOperand(4).getReg();
MCRegister Scratch2 = I->getOperand(4).getReg().asMCReg();
// On Mips64 result of slt is GPR32.
Register Scratch2_32 =
MCRegister Scratch2_32 =
(Size == 8) ? STI->getRegisterInfo()->getSubReg(Scratch2, Mips::sub_32)
: Scratch2;