Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc

will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.

llvm-svn: 117427
This commit is contained in:
Kevin Enderby 2010-10-27 00:59:28 +00:00
parent 6fe024052b
commit ba985d9dd5
2 changed files with 38 additions and 1 deletions

View File

@ -703,6 +703,8 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
.Case("fwait", "wait") .Case("fwait", "wait")
.Case("movzx", "movzb") // FIXME: Not correct. .Case("movzx", "movzb") // FIXME: Not correct.
.Case("fildq", "fildll") .Case("fildq", "fildll")
.Case("fcompi", "fcomip")
.Case("fucompi", "fucomip")
.Default(Name); .Default(Name);
// FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}. // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
@ -991,9 +993,20 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
NameLoc, NameLoc)); NameLoc, NameLoc));
} }
// The assembler accepts this instruction with no operand as a synonym for an
// instruction taking %st(1),%st(0). e.g. "fcompi" -> "fcompi %st(1),st(0)".
if (Name == "fcompi" && Operands.size() == 1) {
Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
NameLoc, NameLoc));
Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(0)"),
NameLoc, NameLoc));
}
// The assembler accepts these instructions with two few operands as a synonym // The assembler accepts these instructions with two few operands as a synonym
// for taking %st(1),%st(0) or X, %st(0). // for taking %st(1),%st(0) or X, %st(0).
if ((Name == "fcomi" || Name == "fucomi") && Operands.size() < 3) { if ((Name == "fcomi" || Name == "fucomi" || Name == "fucompi" ||
Name == "fcompi" ) &&
Operands.size() < 3) {
if (Operands.size() == 1) if (Operands.size() == 1)
Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"), Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
NameLoc, NameLoc)); NameLoc, NameLoc));

View File

@ -702,3 +702,27 @@ pshufw $90, %mm4, %mm0
// CHECK: sidt 4(%eax) // CHECK: sidt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x48,0x04] // CHECK: encoding: [0x0f,0x01,0x48,0x04]
sidtl 4(%eax) sidtl 4(%eax)
// CHECK: fcomip %st(2), %st(0)
// CHECK: encoding: [0xdf,0xf2]
fcompi %st(2),%st
// CHECK: fcomip %st(2), %st(0)
// CHECK: encoding: [0xdf,0xf2]
fcompi %st(2)
// CHECK: fcomip %st(1), %st(0)
// CHECK: encoding: [0xdf,0xf1]
fcompi
// CHECK: fucomip %st(2), %st(0)
// CHECK: encoding: [0xdf,0xea]
fucompi %st(2),%st
// CHECK: fucomip %st(2), %st(0)
// CHECK: encoding: [0xdf,0xea]
fucompi %st(2)
// CHECK: fucomip %st(1), %st(0)
// CHECK: encoding: [0xdf,0xe9]
fucompi