forked from OSchip/llvm-project
[Power9] Implement new vsx instructions: load, store instructions for vector and scalar
We follow the comments mentioned in http://reviews.llvm.org/D16842#344378 to implement this new patch. This patch implements the following vsx instructions: Vector load/store: lxv lxvx lxvb16x lxvl lxvll lxvh8x lxvwsx stxv stxvb16x stxvh8x stxvl stxvll stxvx Scalar load/store: lxsd lxssp lxsibzx lxsihzx stxsd stxssp stxsibx stxsihx 21 instructions Phabricator: http://reviews.llvm.org/D16919 llvm-svn: 262906
This commit is contained in:
Kit Barton
parent
4a795920e3
commit
ba532dc816
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@ -492,6 +492,9 @@ public:
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bool isS16ImmX4() const { return Kind == Expression ||
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(Kind == Immediate && isInt<16>(getImm()) &&
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(getImm() & 3) == 0); }
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bool isS16ImmX16() const { return Kind == Expression ||
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(Kind == Immediate && isInt<16>(getImm()) &&
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(getImm() & 15) == 0); }
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bool isS17Imm() const {
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switch (Kind) {
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case Expression:
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@ -368,6 +368,21 @@ static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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// Decode the memrix16 field (imm, reg), which has the low 12-bits as the
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// displacement with 16-byte aligned, and the next 5 bits as the register #.
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uint64_t Base = Imm >> 12;
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uint64_t Disp = Imm & 0xFFF;
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assert(Base < 32 && "Invalid base register");
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Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4)));
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Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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// The cr bit encoding is 0x80 >> cr_reg_num.
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@ -69,6 +69,9 @@ public:
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unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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@ -249,6 +252,19 @@ unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
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return RegBits;
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}
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unsigned PPCMCCodeEmitter::getMemRIX16Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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// Encode (imm, reg) as a memrix16, which has the low 12-bits as the
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// displacement and the next 5 bits as the register #.
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assert(MI.getOperand(OpNo+1).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;
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const MCOperand &MO = MI.getOperand(OpNo);
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assert(MO.isImm());
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return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
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}
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unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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@ -360,6 +360,21 @@ class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
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let Inst{30-31} = xo;
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}
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// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO]
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class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
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string asmstr, InstrItinClass itin, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, itin> {
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bits<6> XT;
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bits<17> DS_RA;
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let Pattern = pattern;
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let Inst{6-10} = XT{4-0};
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let Inst{11-15} = DS_RA{16-12}; // Register #
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let Inst{16-27} = DS_RA{11-0}; // Displacement.
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let Inst{28} = XT{5};
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let Inst{29-31} = xo;
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}
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// 1.7.6 X-Form
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class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
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@ -635,6 +635,13 @@ def PPCDispRIXOperand : AsmOperandClass {
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def dispRIX : Operand<iPTR> {
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let ParserMatchClass = PPCDispRIXOperand;
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}
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def PPCDispRIX16Operand : AsmOperandClass {
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let Name = "DispRIX16"; let PredicateMethod = "isS16ImmX16";
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let RenderMethod = "addImmOperands";
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}
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def dispRIX16 : Operand<iPTR> {
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let ParserMatchClass = PPCDispRIX16Operand;
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}
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def PPCDispSPE8Operand : AsmOperandClass {
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let Name = "DispSPE8"; let PredicateMethod = "isU8ImmX8";
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let RenderMethod = "addImmOperands";
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@ -673,6 +680,12 @@ def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.
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let EncoderMethod = "getMemRIXEncoding";
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let DecoderMethod = "decodeMemRIXOperands";
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}
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def memrix16 : Operand<iPTR> { // memri, imm is 16-aligned, 12-bit, Inst{16:27}
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let PrintMethod = "printMemRegImm";
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let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg);
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let EncoderMethod = "getMemRIX16Encoding";
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let DecoderMethod = "decodeMemRIX16Operands";
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}
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def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
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let PrintMethod = "printMemRegImm";
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let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg);
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@ -1917,4 +1917,77 @@ let Predicates = [HasP9Vector] in {
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// Round Quad-Precision to Double-Extended Precision (fp80)
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def XSRQPXP : Z23_VT5_R1_VB5_RMC2_EX1<63, 37, 0, "xsrqpxp", []>;
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//===--------------------------------------------------------------------===//
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// Vector/Scalar Load/Store Instructions
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let mayLoad = 1 in {
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// Load Vector
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def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins memrix16:$src),
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"lxv $XT, $src", IIC_LdStLFD, []>;
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// Load DWord
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def LXSD : DSForm_1<57, 2, (outs vrrc:$vD), (ins memrix:$src),
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"lxsd $vD, $src", IIC_LdStLFD, []>;
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// Load SP from src, convert it to DP, and place in dword[0]
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def LXSSP : DSForm_1<57, 3, (outs vrrc:$vD), (ins memrix:$src),
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"lxssp $vD, $src", IIC_LdStLFD, []>;
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// [PO T RA RB XO TX] almost equal to [PO S RA RB XO SX], but has different
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// "out" and "in" dag
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class X_XT6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc,
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RegisterOperand vtype, list<dag> pattern>
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: XX1Form<opcode, xo, (outs vtype:$XT), (ins memrr:$src),
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!strconcat(opc, " $XT, $src"), IIC_LdStLFD, pattern>;
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// Load as Integer Byte/Halfword & Zero Indexed
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def LXSIBZX : X_XT6_RA5_RB5<31, 781, "lxsibzx", vsfrc, []>;
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def LXSIHZX : X_XT6_RA5_RB5<31, 813, "lxsihzx", vsfrc, []>;
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// Load Vector Halfword*8/Byte*16 Indexed
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def LXVH8X : X_XT6_RA5_RB5<31, 812, "lxvh8x" , vsrc, []>;
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def LXVB16X : X_XT6_RA5_RB5<31, 876, "lxvb16x", vsrc, []>;
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// Load Vector Indexed
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def LXVX : X_XT6_RA5_RB5<31, 268, "lxvx" , vsrc, []>;
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// Load Vector (Left-justified) with Length
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def LXVL : X_XT6_RA5_RB5<31, 269, "lxvl" , vsrc, []>;
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def LXVLL : X_XT6_RA5_RB5<31, 301, "lxvll" , vsrc, []>;
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// Load Vector Word & Splat Indexed
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def LXVWSX : X_XT6_RA5_RB5<31, 364, "lxvwsx" , vsrc, []>;
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} // end mayLoad
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let mayStore = 1 in {
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// Store Vector
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def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, memrix16:$dst),
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"stxv $XT, $dst", IIC_LdStSTFD, []>;
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// Store DWord
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def STXSD : DSForm_1<61, 2, (outs), (ins vrrc:$vS, memrix:$dst),
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"stxsd $vS, $dst", IIC_LdStSTFD, []>;
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// Convert DP of dword[0] to SP, and Store to dst
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def STXSSP : DSForm_1<61, 3, (outs), (ins vrrc:$vS, memrix:$dst),
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"stxssp $vS, $dst", IIC_LdStSTFD, []>;
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// [PO S RA RB XO SX]
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class X_XS6_RA5_RB5<bits<6> opcode, bits<10> xo, string opc,
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RegisterOperand vtype, list<dag> pattern>
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: XX1Form<opcode, xo, (outs), (ins vtype:$XT, memrr:$dst),
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!strconcat(opc, " $XT, $dst"), IIC_LdStSTFD, pattern>;
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// Store as Integer Byte/Halfword Indexed
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def STXSIBX : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsfrc, []>;
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def STXSIHX : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsfrc, []>;
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// Store Vector Halfword*8/Byte*16 Indexed
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def STXVH8X : X_XS6_RA5_RB5<31, 940, "stxvh8x" , vsrc, []>;
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def STXVB16X : X_XS6_RA5_RB5<31, 1004, "stxvb16x", vsrc, []>;
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// Store Vector Indexed
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def STXVX : X_XS6_RA5_RB5<31, 396, "stxvx" , vsrc, []>;
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// Store Vector (Left-justified) with Length
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def STXVL : X_XS6_RA5_RB5<31, 397, "stxvl" , vsrc, []>;
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def STXVLL : X_XS6_RA5_RB5<31, 429, "stxvll" , vsrc, []>;
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} // end mayStore
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} // end HasP9Vector
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@ -116,3 +116,82 @@ VSX:
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. Provide builtin?
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(set f128:$vT, (int_ppc_vsx_xsrqpxp f128:$vB))
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- Load/Store Vector: lxv stxv
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. Has likely SDAG match:
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(set v?:$XT, (load ix16addr:$src))
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(set v?:$XT, (store ix16addr:$dst))
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. Need define ix16addr in PPCInstrInfo.td
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ix16addr: 16-byte aligned, see "def memrix16" in PPCInstrInfo.td
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- Load/Store Vector Indexed: lxvx stxvx
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. Has likely SDAG match:
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(set v?:$XT, (load xoaddr:$src))
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(set v?:$XT, (store xoaddr:$dst))
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- Load/Store DWord: lxsd stxsd
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. Similar to lxsdx/stxsdx:
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def LXSDX : XX1Form<31, 588,
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(outs vsfrc:$XT), (ins memrr:$src),
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"lxsdx $XT, $src", IIC_LdStLFD,
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[(set f64:$XT, (load xoaddr:$src))]>;
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. (set f64:$XT, (load ixaddr:$src))
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(set f64:$XT, (store ixaddr:$dst))
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- Load/Store SP, with conversion from/to DP: lxssp stxssp
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. Similar to lxsspx/stxsspx:
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def LXSSPX : XX1Form<31, 524, (outs vssrc:$XT), (ins memrr:$src),
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"lxsspx $XT, $src", IIC_LdStLFD,
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[(set f32:$XT, (load xoaddr:$src))]>;
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. (set f32:$XT, (load ixaddr:$src))
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(set f32:$XT, (store ixaddr:$dst))
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- Load as Integer Byte/Halfword & Zero Indexed: lxsibzx lxsihzx
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. Similar to lxsiwzx:
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def LXSIWZX : XX1Form<31, 12, (outs vsfrc:$XT), (ins memrr:$src),
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"lxsiwzx $XT, $src", IIC_LdStLFD,
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[(set f64:$XT, (PPClfiwzx xoaddr:$src))]>;
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. (set f64:$XT, (PPClfiwzx xoaddr:$src))
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- Store as Integer Byte/Halfword Indexed: stxsibx stxsihx
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. Similar to stxsiwx:
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def STXSIWX : XX1Form<31, 140, (outs), (ins vsfrc:$XT, memrr:$dst),
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"stxsiwx $XT, $dst", IIC_LdStSTFD,
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[(PPCstfiwx f64:$XT, xoaddr:$dst)]>;
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. (PPCstfiwx f64:$XT, xoaddr:$dst)
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- Load Vector Halfword*8/Byte*16 Indexed: lxvh8x lxvb16x
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. Similar to lxvd2x/lxvw4x:
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def LXVD2X : XX1Form<31, 844,
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(outs vsrc:$XT), (ins memrr:$src),
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"lxvd2x $XT, $src", IIC_LdStLFD,
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[(set v2f64:$XT, (int_ppc_vsx_lxvd2x xoaddr:$src))]>;
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. (set v8i16:$XT, (int_ppc_vsx_lxvh8x xoaddr:$src))
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(set v16i8:$XT, (int_ppc_vsx_lxvb16x xoaddr:$src))
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- Store Vector Halfword*8/Byte*16 Indexed: stxvh8x stxvb16x
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. Similar to stxvd2x/stxvw4x:
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def STXVD2X : XX1Form<31, 972,
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(outs), (ins vsrc:$XT, memrr:$dst),
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"stxvd2x $XT, $dst", IIC_LdStSTFD,
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[(store v2f64:$XT, xoaddr:$dst)]>;
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. (store v8i16:$XT, xoaddr:$dst)
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(store v16i8:$XT, xoaddr:$dst)
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- Load/Store Vector (Left-justified) with Length: lxvl lxvll stxvl stxvll
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. Likely needs an intrinsic
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. (set v?:$XT, (int_ppc_vsx_lxvl xoaddr:$src))
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(set v?:$XT, (int_ppc_vsx_lxvll xoaddr:$src))
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. (int_ppc_vsx_stxvl xoaddr:$dst))
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(int_ppc_vsx_stxvll xoaddr:$dst))
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- Load Vector Word & Splat Indexed: lxvwsx
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. Likely needs an intrinsic
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. (set v?:$XT, (int_ppc_vsx_lxvwsx xoaddr:$src))
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@ -625,3 +625,78 @@
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# CHECK: xsrqpxp 1, 7, 27, 2
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0xfc 0xe1 0xdc 0x4a
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# CHECK: lxv 61, 32752(31)
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0xf7 0xbf 0x7f 0xf9
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# CHECK: lxv 61, -32768(0)
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0xf7 0xa0 0x80 0x09
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# CHECK: stxv 61, 32752(31)
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0xf7 0xbf 0x7f 0xfd
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# CHECK: stxv 61, -32768(0)
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0xf7 0xa0 0x80 0x0d
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# CHECK: lxsd 31, -32768(0)
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0xe7 0xe0 0x80 0x02
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# CHECK: lxsd 31, 32764(12)
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0xe7 0xec 0x7f 0xfe
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# CHECK: lxssp 31, -32768(0)
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0xe7 0xe0 0x80 0x03
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# CHECK: lxssp 31, 32764(12)
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0xe7 0xec 0x7f 0xff
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# CHECK: stxsd 31, 32764(12)
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0xf7 0xec 0x7f 0xfe
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# CHECK: stxssp 31, -32768(0)
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0xf7 0xe0 0x80 0x03
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# CHECK: lxvx 57, 12, 27
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0x7f 0x2c 0xda 0x19
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# CHECK: lxsibzx 57, 12, 27
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0x7f 0x2c 0xde 0x1b
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# CHECK: lxsihzx 57, 12, 27
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0x7f 0x2c 0xde 0x5b
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# CHECK: lxvb16x 57, 12, 27
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0x7f 0x2c 0xde 0xd9
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# CHECK: lxvh8x 57, 12, 27
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0x7f 0x2c 0xde 0x59
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# CHECK: lxvl 57, 12, 27
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0x7f 0x2c 0xda 0x1b
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# CHECK: lxvll 57, 12, 27
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0x7f 0x2c 0xda 0x5b
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# CHECK: lxvwsx 57, 12, 27
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0x7f 0x2c 0xda 0xd9
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# CHECK: stxsibx 57, 12, 27
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0x7f 0x2c 0xdf 0x1b
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# CHECK: stxsihx 57, 12, 27
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0x7f 0x2c 0xdf 0x5b
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# CHECK: stxvh8x 57, 12, 27
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0x7f 0x2c 0xdf 0x59
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# CHECK: stxvb16x 57, 12, 27
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0x7f 0x2c 0xdf 0xd9
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# CHECK: stxvx 57, 12, 27
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0x7f 0x2c 0xdb 0x19
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# CHECK: stxvl 57, 12, 27
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0x7f 0x2c 0xdb 0x1b
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# CHECK: stxvll 57, 12, 27
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0x7f 0x2c 0xdb 0x5b
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@ -657,3 +657,104 @@
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# CHECK-BE: xsrqpxp 1, 7, 27, 2 # encoding: [0xfc,0xe1,0xdc,0x4a]
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# CHECK-LE: xsrqpxp 1, 7, 27, 2 # encoding: [0x4a,0xdc,0xe1,0xfc]
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xsrqpxp 1, 7, 27, 2
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# Load/Store Vector, test maximum and minimum displacement value
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||||
# CHECK-BE: lxv 61, 32752(31) # encoding: [0xf7,0xbf,0x7f,0xf9]
|
||||
# CHECK-LE: lxv 61, 32752(31) # encoding: [0xf9,0x7f,0xbf,0xf7]
|
||||
lxv 61, 32752(31)
|
||||
# CHECK-BE: lxv 61, -32768(0) # encoding: [0xf7,0xa0,0x80,0x09]
|
||||
# CHECK-LE: lxv 61, -32768(0) # encoding: [0x09,0x80,0xa0,0xf7]
|
||||
lxv 61, -32768(0)
|
||||
# CHECK-BE: stxv 61, 32752(31) # encoding: [0xf7,0xbf,0x7f,0xfd]
|
||||
# CHECK-LE: stxv 61, 32752(31) # encoding: [0xfd,0x7f,0xbf,0xf7]
|
||||
stxv 61, 32752(31)
|
||||
# CHECK-BE: stxv 61, -32768(0) # encoding: [0xf7,0xa0,0x80,0x0d]
|
||||
# CHECK-LE: stxv 61, -32768(0) # encoding: [0x0d,0x80,0xa0,0xf7]
|
||||
stxv 61, -32768(0)
|
||||
|
||||
# Load/Store DWord
|
||||
# CHECK-BE: lxsd 31, -32768(0) # encoding: [0xe7,0xe0,0x80,0x02]
|
||||
# CHECK-LE: lxsd 31, -32768(0) # encoding: [0x02,0x80,0xe0,0xe7]
|
||||
lxsd 31, -32768(0)
|
||||
# CHECK-BE: lxsd 31, 32764(12) # encoding: [0xe7,0xec,0x7f,0xfe]
|
||||
# CHECK-LE: lxsd 31, 32764(12) # encoding: [0xfe,0x7f,0xec,0xe7]
|
||||
lxsd 31, 32764(12)
|
||||
# CHECK-BE: stxsd 31, 32764(12) # encoding: [0xf7,0xec,0x7f,0xfe]
|
||||
# CHECK-LE: stxsd 31, 32764(12) # encoding: [0xfe,0x7f,0xec,0xf7]
|
||||
stxsd 31, 32764(12)
|
||||
|
||||
# Load SP from src, convert it to DP, and place in dword[0]
|
||||
# CHECK-BE: lxssp 31, -32768(0) # encoding: [0xe7,0xe0,0x80,0x03]
|
||||
# CHECK-LE: lxssp 31, -32768(0) # encoding: [0x03,0x80,0xe0,0xe7]
|
||||
lxssp 31, -32768(0)
|
||||
# CHECK-BE: lxssp 31, 32764(12) # encoding: [0xe7,0xec,0x7f,0xff]
|
||||
# CHECK-LE: lxssp 31, 32764(12) # encoding: [0xff,0x7f,0xec,0xe7]
|
||||
lxssp 31, 32764(12)
|
||||
|
||||
# Convert DP of dword[0] to SP, and Store to dst
|
||||
# CHECK-BE: stxssp 31, -32768(0) # encoding: [0xf7,0xe0,0x80,0x03]
|
||||
# CHECK-LE: stxssp 31, -32768(0) # encoding: [0x03,0x80,0xe0,0xf7]
|
||||
stxssp 31, -32768(0)
|
||||
|
||||
# Load as Integer Byte/Halfword & Zero Indexed
|
||||
# CHECK-BE: lxsibzx 57, 12, 27 # encoding: [0x7f,0x2c,0xde,0x1b]
|
||||
# CHECK-LE: lxsibzx 57, 12, 27 # encoding: [0x1b,0xde,0x2c,0x7f]
|
||||
lxsibzx 57, 12, 27
|
||||
# CHECK-BE: lxsihzx 57, 12, 27 # encoding: [0x7f,0x2c,0xde,0x5b]
|
||||
# CHECK-LE: lxsihzx 57, 12, 27 # encoding: [0x5b,0xde,0x2c,0x7f]
|
||||
lxsihzx 57, 12, 27
|
||||
|
||||
# Load Vector Halfword*8/Byte*16 Indexed
|
||||
# CHECK-BE: lxvh8x 57, 12, 27 # encoding: [0x7f,0x2c,0xde,0x59]
|
||||
# CHECK-LE: lxvh8x 57, 12, 27 # encoding: [0x59,0xde,0x2c,0x7f]
|
||||
lxvh8x 57, 12, 27
|
||||
# CHECK-BE: lxvb16x 57, 12, 27 # encoding: [0x7f,0x2c,0xde,0xd9]
|
||||
# CHECK-LE: lxvb16x 57, 12, 27 # encoding: [0xd9,0xde,0x2c,0x7f]
|
||||
lxvb16x 57, 12, 27
|
||||
|
||||
# Load Vector Indexed
|
||||
# CHECK-BE: lxvx 57, 12, 27 # encoding: [0x7f,0x2c,0xda,0x19]
|
||||
# CHECK-LE: lxvx 57, 12, 27 # encoding: [0x19,0xda,0x2c,0x7f]
|
||||
lxvx 57, 12, 27
|
||||
|
||||
# Load Vector (Left-justified) with Length
|
||||
# CHECK-BE: lxvl 57, 12, 27 # encoding: [0x7f,0x2c,0xda,0x1b]
|
||||
# CHECK-LE: lxvl 57, 12, 27 # encoding: [0x1b,0xda,0x2c,0x7f]
|
||||
lxvl 57, 12, 27
|
||||
# CHECK-BE: lxvll 57, 12, 27 # encoding: [0x7f,0x2c,0xda,0x5b]
|
||||
# CHECK-LE: lxvll 57, 12, 27 # encoding: [0x5b,0xda,0x2c,0x7f]
|
||||
lxvll 57, 12, 27
|
||||
|
||||
# Load Vector Word & Splat Indexed
|
||||
# CHECK-BE: lxvwsx 57, 12, 27 # encoding: [0x7f,0x2c,0xda,0xd9]
|
||||
# CHECK-LE: lxvwsx 57, 12, 27 # encoding: [0xd9,0xda,0x2c,0x7f]
|
||||
lxvwsx 57, 12, 27
|
||||
|
||||
# Store as Integer Byte/Halfword Indexed
|
||||
# CHECK-BE: stxsibx 57, 12, 27 # encoding: [0x7f,0x2c,0xdf,0x1b]
|
||||
# CHECK-LE: stxsibx 57, 12, 27 # encoding: [0x1b,0xdf,0x2c,0x7f]
|
||||
stxsibx 57, 12, 27
|
||||
# CHECK-BE: stxsihx 57, 12, 27 # encoding: [0x7f,0x2c,0xdf,0x5b]
|
||||
# CHECK-LE: stxsihx 57, 12, 27 # encoding: [0x5b,0xdf,0x2c,0x7f]
|
||||
stxsihx 57, 12, 27
|
||||
|
||||
# Store Vector Halfword*8/Byte*16 Indexed
|
||||
# CHECK-BE: stxvh8x 57, 12, 27 # encoding: [0x7f,0x2c,0xdf,0x59]
|
||||
# CHECK-LE: stxvh8x 57, 12, 27 # encoding: [0x59,0xdf,0x2c,0x7f]
|
||||
stxvh8x 57, 12, 27
|
||||
# CHECK-BE: stxvb16x 57, 12, 27 # encoding: [0x7f,0x2c,0xdf,0xd9]
|
||||
# CHECK-LE: stxvb16x 57, 12, 27 # encoding: [0xd9,0xdf,0x2c,0x7f]
|
||||
stxvb16x 57, 12, 27
|
||||
|
||||
# Store Vector Indexed
|
||||
# CHECK-BE: stxvx 57, 12, 27 # encoding: [0x7f,0x2c,0xdb,0x19]
|
||||
# CHECK-LE: stxvx 57, 12, 27 # encoding: [0x19,0xdb,0x2c,0x7f]
|
||||
stxvx 57, 12, 27
|
||||
|
||||
# Store Vector (Left-justified) with Length
|
||||
# CHECK-BE: stxvl 57, 12, 27 # encoding: [0x7f,0x2c,0xdb,0x1b]
|
||||
# CHECK-LE: stxvl 57, 12, 27 # encoding: [0x1b,0xdb,0x2c,0x7f]
|
||||
stxvl 57, 12, 27
|
||||
# CHECK-BE: stxvll 57, 12, 27 # encoding: [0x7f,0x2c,0xdb,0x5b]
|
||||
# CHECK-LE: stxvll 57, 12, 27 # encoding: [0x5b,0xdb,0x2c,0x7f]
|
||||
stxvll 57, 12, 27
|
||||
|
|
|
|||
Loading…
Reference in New Issue