forked from OSchip/llvm-project
with the new code we can thread non-instruction values. This
allows us to handle the test10 testcase. llvm-svn: 86924
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@ -518,8 +518,13 @@ bool JumpThreading::ProcessBlock(BasicBlock *BB) {
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}
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// All the rest of our checks depend on the condition being an instruction.
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if (CondInst == 0)
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if (CondInst == 0) {
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// FIXME: Unify this with code below.
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if (LVI && ProcessThreadableEdges(Condition, BB))
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return true;
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return false;
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}
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// See if this is a phi node in the current block.
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if (PHINode *PN = dyn_cast<PHINode>(CondInst))
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@ -285,12 +285,50 @@ F2:
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; CHECK: @test10
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declare i32 @test10f1()
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declare i32 @test10f2()
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declare void @test10f3()
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;; Non-local condition threading.
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define i32 @test10(i1 %cond) {
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; CHECK: @test10
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; CHECK-NEXT: br i1 %cond, label %T2, label %F2
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br i1 %cond, label %T1, label %F1
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T1:
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%v1 = call i32 @test10f1()
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br label %Merge
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; CHECK: %v1 = call i32 @test10f1()
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; CHECK-NEXT: call void @f3()
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; CHeCK-NEXT: ret i32 %v1
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F1:
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%v2 = call i32 @test10f2()
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br label %Merge
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Merge:
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%B = phi i32 [%v1, %T1], [%v2, %F1]
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br i1 %cond, label %T2, label %F2
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T2:
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call void @f3()
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ret i32 %B
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F2:
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ret i32 %B
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}
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;;; Duplicate condition to avoid xor of cond.
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;;; TODO: Make this happen.
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define i32 @test10(i1 %cond, i1 %cond2) {
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define i32 @test11(i1 %cond, i1 %cond2) {
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Entry:
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; CHECK: @test10
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; CHECK: @test11
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%v1 = call i32 @f1()
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br i1 %cond, label %Merge, label %F1
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