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Formatting. 

llvm-svn: 63199
This commit is contained in:
Duncan Sands 2009-01-28 14:42:54 +00:00
parent 5a913d61e3
commit ba21b7d57a
1 changed files with 5 additions and 8 deletions
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7
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
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@ -374,11 +374,8 @@ unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
/// larger then ValueVT then AssertOp can be used to specify whether the extra
/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
/// (ISD::AssertSext).
static SDValue getCopyFromParts(SelectionDAG &DAG,
const SDValue *Parts,
unsigned NumParts,
MVT PartVT,
MVT ValueVT,
static SDValue getCopyFromParts(SelectionDAG &DAG, const SDValue *Parts,
unsigned NumParts, MVT PartVT, MVT ValueVT,
ISD::NodeType AssertOp = ISD::DELETED_NODE) {
assert(NumParts > 0 && "No parts to assemble!");
const TargetLowering &TLI = DAG.getTargetLoweringInfo();