forked from OSchip/llvm-project
ARM/AArch64: Attach the FrameSetup MIFlag to CFI instructions.
Debug info marks the first instruction without the FrameSetup flag as being the end of the function prologue. Any CFI instructions in the middle of the function prologue would cause debug info to end the prologue too early and worse, attach the line number of the CFI instruction, which incidentally is often 0. llvm-svn: 224294
This commit is contained in:
Adrian Prantl
parent
d9a00a9c38
commit
b9fa945d51
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@ -1117,8 +1117,12 @@ static DebugLoc findPrologueEndLoc(const MachineFunction *MF) {
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for (const auto &MBB : *MF)
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for (const auto &MI : MBB)
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if (!MI.isDebugValue() && !MI.getFlag(MachineInstr::FrameSetup) &&
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!MI.getDebugLoc().isUnknown())
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!MI.getDebugLoc().isUnknown()) {
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// Did the target forget to set the FrameSetup flag for CFI insns?
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assert(!MI.isCFIInstruction() &&
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"First non-frame-setup instruction is a CFI instruction.");
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return MI.getDebugLoc();
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}
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return DebugLoc();
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}
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@ -196,7 +196,8 @@ void AArch64FrameLowering::emitCalleeSavedFrameMoves(
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unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
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nullptr, DwarfReg, Offset - TotalSkipped));
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BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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.addCFIIndex(CFIIndex)
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.setMIFlags(MachineInstr::FrameSetup);
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}
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}
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@ -234,7 +235,8 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF) const {
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unsigned CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createDefCfaOffset(FrameLabel, -NumBytes));
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BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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.addCFIIndex(CFIIndex)
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.setMIFlags(MachineInstr::FrameSetup);
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} else if (NumBytes) {
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++NumRedZoneFunctions;
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}
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@ -377,26 +379,30 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF) const {
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unsigned CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createDefCfa(nullptr, Reg, 2 * StackGrowth));
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BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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.addCFIIndex(CFIIndex)
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.setMIFlags(MachineInstr::FrameSetup);
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// Record the location of the stored LR
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unsigned LR = RegInfo->getDwarfRegNum(AArch64::LR, true);
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CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createOffset(nullptr, LR, StackGrowth));
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BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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.addCFIIndex(CFIIndex)
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.setMIFlags(MachineInstr::FrameSetup);
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// Record the location of the stored FP
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CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createOffset(nullptr, Reg, 2 * StackGrowth));
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BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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.addCFIIndex(CFIIndex)
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.setMIFlags(MachineInstr::FrameSetup);
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} else {
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// Encode the stack size of the leaf function.
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unsigned CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createDefCfaOffset(nullptr, -MFI->getStackSize()));
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BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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.addCFIIndex(CFIIndex)
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.setMIFlags(MachineInstr::FrameSetup);
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}
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// Now emit the moves for whatever callee saved regs we have.
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@ -203,7 +203,9 @@ struct StackAdjustingInsts {
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unsigned CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
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BuildMI(MBB, std::next(Info.I), dl,
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TII.get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
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TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex)
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.setMIFlags(MachineInstr::FrameSetup);
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}
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}
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};
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@ -451,13 +453,15 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
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nullptr, MRI->getDwarfRegNum(FramePtr, true),
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-(ArgRegsSaveSize - FramePtrOffsetInPush)));
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BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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.addCFIIndex(CFIIndex)
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.setMIFlags(MachineInstr::FrameSetup);
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} else {
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unsigned CFIIndex =
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MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
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nullptr, MRI->getDwarfRegNum(FramePtr, true)));
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BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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.addCFIIndex(CFIIndex)
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.setMIFlags(MachineInstr::FrameSetup);
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}
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}
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@ -491,7 +495,8 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
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CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
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nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
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BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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.addCFIIndex(CFIIndex)
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.setMIFlags(MachineInstr::FrameSetup);
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break;
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}
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}
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@ -514,7 +519,8 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
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unsigned CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
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BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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.addCFIIndex(CFIIndex)
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.setMIFlags(MachineInstr::FrameSetup);
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}
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break;
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}
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@ -535,7 +541,8 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF) const {
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unsigned CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
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BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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.addCFIIndex(CFIIndex)
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.setMIFlags(MachineInstr::FrameSetup);
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}
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}
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}
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@ -0,0 +1,112 @@
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; struct A {
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; A();
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; virtual ~A();
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; };
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; struct B : A {
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; B();
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; virtual ~B();
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; };
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; B::B() {}
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; CHECK: __ZN1BC1Ev:
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; CHECK: .loc 1 [[@LINE-2]] 0 prologue_end
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; CHECK-NOT: .loc 1 0 0 prologue_end
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; The location of the prologue_end marker should not be affected by the presence
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; of CFI instructions.
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; RUN: llc -O0 -filetype=asm < %s | FileCheck %s
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; ModuleID = 'test1.cpp'
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-apple-ios"
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%struct.B = type { %struct.A }
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%struct.A = type { i32 (...)** }
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@_ZTV1B = external unnamed_addr constant [4 x i8*]
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; Function Attrs: nounwind
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define %struct.B* @_ZN1BC2Ev(%struct.B* %this) unnamed_addr #0 align 2 {
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entry:
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tail call void @llvm.dbg.value(metadata %struct.B* %this, i64 0, metadata !30, metadata !38), !dbg !39
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%0 = getelementptr inbounds %struct.B* %this, i64 0, i32 0, !dbg !40
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%call = tail call %struct.A* @_ZN1AC2Ev(%struct.A* %0) #3, !dbg !40
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%1 = getelementptr inbounds %struct.B* %this, i64 0, i32 0, i32 0, !dbg !40
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store i32 (...)** bitcast (i8** getelementptr inbounds ([4 x i8*]* @_ZTV1B, i64 0, i64 2) to i32 (...)**), i32 (...)*** %1, align 8, !dbg !40, !tbaa !41
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ret %struct.B* %this, !dbg !40
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}
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declare %struct.A* @_ZN1AC2Ev(%struct.A*)
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; Function Attrs: nounwind
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define %struct.B* @_ZN1BC1Ev(%struct.B* %this) unnamed_addr #0 align 2 {
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entry:
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tail call void @llvm.dbg.value(metadata %struct.B* %this, i64 0, metadata !34, metadata !38), !dbg !44
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tail call void @llvm.dbg.value(metadata %struct.B* %this, i64 0, metadata !45, metadata !38) #3, !dbg !47
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%0 = getelementptr inbounds %struct.B* %this, i64 0, i32 0, !dbg !48
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%call.i = tail call %struct.A* @_ZN1AC2Ev(%struct.A* %0) #3, !dbg !48
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%1 = getelementptr inbounds %struct.B* %this, i64 0, i32 0, i32 0, !dbg !48
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store i32 (...)** bitcast (i8** getelementptr inbounds ([4 x i8*]* @_ZTV1B, i64 0, i64 2) to i32 (...)**), i32 (...)*** %1, align 8, !dbg !48, !tbaa !41
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ret %struct.B* %this, !dbg !46
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}
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; Function Attrs: nounwind readnone
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declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2
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attributes #0 = { nounwind }
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attributes #2 = { nounwind readnone }
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attributes #3 = { nounwind }
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!llvm.dbg.cu = !{!0}
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!llvm.module.flags = !{!35, !36}
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!llvm.ident = !{!37}
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!0 = !{!"0x11\004\00clang version 3.6.0 (trunk 224279) (llvm/trunk 224283)\001\00\000\00\001", !1, !2, !3, !27, !2, !2} ; [ DW_TAG_compile_unit ] [<stdin>] [DW_LANG_C_plus_plus]
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!1 = !{!"<stdin>", !""}
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!2 = !{}
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!3 = !{!4, !13}
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!4 = !{!"0x13\00B\005\0064\0064\000\000\000", !5, null, null, !6, !"_ZTS1A", null, !"_ZTS1B"} ; [ DW_TAG_structure_type ] [B] [line 5, size 64, align 64, offset 0] [def] [from ]
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!5 = !{!"test1.cpp", !""}
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!6 = !{!7, !8, !12}
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!7 = !{!"0x1c\00\000\000\000\000\000", null, !"_ZTS1B", !"_ZTS1A"} ; [ DW_TAG_inheritance ] [line 0, size 0, align 0, offset 0] [from _ZTS1A]
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!8 = !{!"0x2e\00B\00B\00\006\000\000\000\000\00256\001\006", !5, !"_ZTS1B", !9, null, null, null, null, null} ; [ DW_TAG_subprogram ] [line 6] [B]
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!9 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !10, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
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!10 = !{null, !11}
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!11 = !{!"0xf\00\000\0064\0064\000\001088\00", null, null, !"_ZTS1B"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1B]
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!12 = !{!"0x2e\00~B\00~B\00\007\000\000\001\000\00256\001\007", !5, !"_ZTS1B", !9, !"_ZTS1B", null, null, null, null} ; [ DW_TAG_subprogram ] [line 7] [~B]
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!13 = !{!"0x13\00A\001\0064\0064\000\000\000", !5, null, null, !14, !"_ZTS1A", null, !"_ZTS1A"} ; [ DW_TAG_structure_type ] [A] [line 1, size 64, align 64, offset 0] [def] [from ]
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!14 = !{!15, !22, !26}
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!15 = !{!"0xd\00_vptr$A\000\0064\000\000\0064", !5, !16, !17} ; [ DW_TAG_member ] [_vptr$A] [line 0, size 64, align 0, offset 0] [artificial] [from ]
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!16 = !{!"0x29", !5} ; [ DW_TAG_file_type ] [test1.cpp]
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!17 = !{!"0xf\00\000\0064\000\000\000", null, null, !18} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 0, offset 0] [from __vtbl_ptr_type]
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!18 = !{!"0xf\00__vtbl_ptr_type\000\0064\000\000\000", null, null, !19} ; [ DW_TAG_pointer_type ] [__vtbl_ptr_type] [line 0, size 64, align 0, offset 0] [from ]
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!19 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !20, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
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!20 = !{!21}
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!21 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
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!22 = !{!"0x2e\00A\00A\00\002\000\000\000\000\00256\001\002", !5, !"_ZTS1A", !23, null, null, null, null, null} ; [ DW_TAG_subprogram ] [line 2] [A]
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!23 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !24, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
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!24 = !{null, !25}
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!25 = !{!"0xf\00\000\0064\0064\000\001088\00", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [artificial] [from _ZTS1A]
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!26 = !{!"0x2e\00~A\00~A\00\003\000\000\001\000\00256\001\003", !5, !"_ZTS1A", !23, !"_ZTS1A", null, null, null, null} ; [ DW_TAG_subprogram ] [line 3] [~A]
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!27 = !{!28, !32}
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!28 = !{!"0x2e\00B\00B\00_ZN1BC2Ev\009\000\001\000\000\00256\001\009", !5, !"_ZTS1B", !9, null, %struct.B* (%struct.B*)* @_ZN1BC2Ev, null, !8, !29} ; [ DW_TAG_subprogram ] [line 9] [def] [B]
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!29 = !{!30}
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!30 = !{!"0x101\00this\0016777216\001088", !28, null, !31} ; [ DW_TAG_arg_variable ] [this] [line 0]
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!31 = !{!"0xf\00\000\0064\0064\000\000", null, null, !"_ZTS1B"} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _ZTS1B]
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!32 = !{!"0x2e\00B\00B\00_ZN1BC1Ev\009\000\001\000\000\00256\001\009", !5, !"_ZTS1B", !9, null, %struct.B* (%struct.B*)* @_ZN1BC1Ev, null, !8, !33} ; [ DW_TAG_subprogram ] [line 9] [def] [B]
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!33 = !{!34}
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!34 = !{!"0x101\00this\0016777216\001088", !32, null, !31} ; [ DW_TAG_arg_variable ] [this] [line 0]
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!35 = !{i32 2, !"Dwarf Version", i32 4}
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!36 = !{i32 2, !"Debug Info Version", i32 2}
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!37 = !{!"clang version 3.6.0 (trunk 224279) (llvm/trunk 224283)"}
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!38 = !{!"0x102"} ; [ DW_TAG_expression ]
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!39 = !{i32 0, i32 0, !28, null}
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!40 = !{i32 9, i32 0, !28, null}
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!41 = !{!42, !42, i64 0}
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!42 = !{!"vtable pointer", !43, i64 0}
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!43 = !{!"Simple C/C++ TBAA"}
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!44 = !{i32 0, i32 0, !32, null}
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!45 = !{!"0x101\00this\0016777216\001088", !28, null, !31, !46} ; [ DW_TAG_arg_variable ] [this] [line 0]
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!46 = !{i32 9, i32 0, !32, null}
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!47 = !{i32 0, i32 0, !28, !46}
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!48 = !{i32 9, i32 0, !28, !46}
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@ -0,0 +1,114 @@
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; struct A {
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; A();
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; virtual ~A();
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; };
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; struct B : A {
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; B();
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; virtual ~B();
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; };
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; B::B() {}
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; CHECK: __ZN1BC1Ev:
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; CHECK: .loc 1 [[@LINE-2]] 0 prologue_end
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; CHECK-NOT: .loc 1 0 0 prologue_end
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; The location of the prologue_end marker should not be affected by the presence
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; of CFI instructions.
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; RUN: llc -O0 -filetype=asm < %s | FileCheck %s
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; ModuleID = 'test1.cpp'
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target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
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target triple = "thumbv7-apple-ios"
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%struct.B = type { %struct.A }
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%struct.A = type { i32 (...)** }
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@_ZTV1B = external unnamed_addr constant [4 x i8*]
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; Function Attrs: nounwind
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define %struct.B* @_ZN1BC2Ev(%struct.B* %this) unnamed_addr #0 align 2 {
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entry:
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tail call void @llvm.dbg.value(metadata %struct.B* %this, i64 0, metadata !30, metadata !40), !dbg !41
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%0 = getelementptr inbounds %struct.B* %this, i32 0, i32 0, !dbg !42
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%call = tail call %struct.A* @_ZN1AC2Ev(%struct.A* %0) #3, !dbg !42
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%1 = getelementptr inbounds %struct.B* %this, i32 0, i32 0, i32 0, !dbg !42
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store i32 (...)** bitcast (i8** getelementptr inbounds ([4 x i8*]* @_ZTV1B, i32 0, i32 2) to i32 (...)**), i32 (...)*** %1, align 4, !dbg !42, !tbaa !43
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ret %struct.B* %this, !dbg !42
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}
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declare %struct.A* @_ZN1AC2Ev(%struct.A*)
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; Function Attrs: nounwind
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define %struct.B* @_ZN1BC1Ev(%struct.B* %this) unnamed_addr #0 align 2 {
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entry:
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tail call void @llvm.dbg.value(metadata %struct.B* %this, i64 0, metadata !34, metadata !40), !dbg !46
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tail call void @llvm.dbg.value(metadata %struct.B* %this, i64 0, metadata !47, metadata !40) #3, !dbg !49
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%0 = getelementptr inbounds %struct.B* %this, i32 0, i32 0, !dbg !50
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%call.i = tail call %struct.A* @_ZN1AC2Ev(%struct.A* %0) #3, !dbg !50
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%1 = getelementptr inbounds %struct.B* %this, i32 0, i32 0, i32 0, !dbg !50
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store i32 (...)** bitcast (i8** getelementptr inbounds ([4 x i8*]* @_ZTV1B, i32 0, i32 2) to i32 (...)**), i32 (...)*** %1, align 4, !dbg !50, !tbaa !43
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ret %struct.B* %this, !dbg !48
|
||||
}
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #2 = { nounwind readnone }
|
||||
attributes #3 = { nounwind }
|
||||
|
||||
!llvm.dbg.cu = !{!0}
|
||||
!llvm.module.flags = !{!35, !36, !37, !38}
|
||||
!llvm.ident = !{!39}
|
||||
|
||||
!0 = !{!"0x11\004\00clang version 3.6.0 (trunk 224279) (llvm/trunk 224283)\001\00\000\00\001", !1, !2, !3, !27, !2, !2} ; [ DW_TAG_compile_unit ] [<stdin>] [DW_LANG_C_plus_plus]
|
||||
!1 = !{!"<stdin>", !""}
|
||||
!2 = !{}
|
||||
!3 = !{!4, !13}
|
||||
!4 = !{!"0x13\00B\005\0032\0032\000\000\000", !5, null, null, !6, !"_ZTS1A", null, !"_ZTS1B"} ; [ DW_TAG_structure_type ] [B] [line 5, size 32, align 32, offset 0] [def] [from ]
|
||||
!5 = !{!"test1.cpp", !""}
|
||||
!6 = !{!7, !8, !12}
|
||||
!7 = !{!"0x1c\00\000\000\000\000\000", null, !"_ZTS1B", !"_ZTS1A"} ; [ DW_TAG_inheritance ] [line 0, size 0, align 0, offset 0] [from _ZTS1A]
|
||||
!8 = !{!"0x2e\00B\00B\00\006\000\000\000\000\00256\001\006", !5, !"_ZTS1B", !9, null, null, null, null, null} ; [ DW_TAG_subprogram ] [line 6] [B]
|
||||
!9 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !10, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
|
||||
!10 = !{null, !11}
|
||||
!11 = !{!"0xf\00\000\0032\0032\000\001088\00", null, null, !"_ZTS1B"} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [artificial] [from _ZTS1B]
|
||||
!12 = !{!"0x2e\00~B\00~B\00\007\000\000\001\000\00256\001\007", !5, !"_ZTS1B", !9, !"_ZTS1B", null, null, null, null} ; [ DW_TAG_subprogram ] [line 7] [~B]
|
||||
!13 = !{!"0x13\00A\001\0032\0032\000\000\000", !5, null, null, !14, !"_ZTS1A", null, !"_ZTS1A"} ; [ DW_TAG_structure_type ] [A] [line 1, size 32, align 32, offset 0] [def] [from ]
|
||||
!14 = !{!15, !22, !26}
|
||||
!15 = !{!"0xd\00_vptr$A\000\0032\000\000\0064", !5, !16, !17} ; [ DW_TAG_member ] [_vptr$A] [line 0, size 32, align 0, offset 0] [artificial] [from ]
|
||||
!16 = !{!"0x29", !5} ; [ DW_TAG_file_type ] [test1.cpp]
|
||||
!17 = !{!"0xf\00\000\0032\000\000\000", null, null, !18} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 0, offset 0] [from __vtbl_ptr_type]
|
||||
!18 = !{!"0xf\00__vtbl_ptr_type\000\0032\000\000\000", null, null, !19} ; [ DW_TAG_pointer_type ] [__vtbl_ptr_type] [line 0, size 32, align 0, offset 0] [from ]
|
||||
!19 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !20, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
|
||||
!20 = !{!21}
|
||||
!21 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed]
|
||||
!22 = !{!"0x2e\00A\00A\00\002\000\000\000\000\00256\001\002", !5, !"_ZTS1A", !23, null, null, null, null, null} ; [ DW_TAG_subprogram ] [line 2] [A]
|
||||
!23 = !{!"0x15\00\000\000\000\000\000\000", null, null, null, !24, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ]
|
||||
!24 = !{null, !25}
|
||||
!25 = !{!"0xf\00\000\0032\0032\000\001088\00", null, null, !"_ZTS1A"} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [artificial] [from _ZTS1A]
|
||||
!26 = !{!"0x2e\00~A\00~A\00\003\000\000\001\000\00256\001\003", !5, !"_ZTS1A", !23, !"_ZTS1A", null, null, null, null} ; [ DW_TAG_subprogram ] [line 3] [~A]
|
||||
!27 = !{!28, !32}
|
||||
!28 = !{!"0x2e\00B\00B\00_ZN1BC2Ev\009\000\001\000\000\00256\001\009", !5, !"_ZTS1B", !9, null, %struct.B* (%struct.B*)* @_ZN1BC2Ev, null, !8, !29} ; [ DW_TAG_subprogram ] [line 9] [def] [B]
|
||||
!29 = !{!30}
|
||||
!30 = !{!"0x101\00this\0016777216\001088", !28, null, !31} ; [ DW_TAG_arg_variable ] [this] [line 0]
|
||||
!31 = !{!"0xf\00\000\0032\0032\000\000", null, null, !"_ZTS1B"} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from _ZTS1B]
|
||||
!32 = !{!"0x2e\00B\00B\00_ZN1BC1Ev\009\000\001\000\000\00256\001\009", !5, !"_ZTS1B", !9, null, %struct.B* (%struct.B*)* @_ZN1BC1Ev, null, !8, !33} ; [ DW_TAG_subprogram ] [line 9] [def] [B]
|
||||
!33 = !{!34}
|
||||
!34 = !{!"0x101\00this\0016777216\001088", !32, null, !31} ; [ DW_TAG_arg_variable ] [this] [line 0]
|
||||
!35 = !{i32 2, !"Dwarf Version", i32 4}
|
||||
!36 = !{i32 2, !"Debug Info Version", i32 2}
|
||||
!37 = !{i32 1, !"wchar_size", i32 4}
|
||||
!38 = !{i32 1, !"min_enum_size", i32 4}
|
||||
!39 = !{!"clang version 3.6.0 (trunk 224279) (llvm/trunk 224283)"}
|
||||
!40 = !{!"0x102"} ; [ DW_TAG_expression ]
|
||||
!41 = !{i32 0, i32 0, !28, null}
|
||||
!42 = !{i32 9, i32 0, !28, null}
|
||||
!43 = !{!44, !44, i64 0}
|
||||
!44 = !{!"vtable pointer", !45, i64 0}
|
||||
!45 = !{!"Simple C/C++ TBAA"}
|
||||
!46 = !{i32 0, i32 0, !32, null}
|
||||
!47 = !{!"0x101\00this\0016777216\001088", !28, null, !31, !48} ; [ DW_TAG_arg_variable ] [this] [line 0]
|
||||
!48 = !{i32 9, i32 0, !32, null}
|
||||
!49 = !{i32 0, i32 0, !28, !48}
|
||||
!50 = !{i32 9, i32 0, !28, !48}
|
||||
Loading…
Reference in New Issue