forked from OSchip/llvm-project
AArch64: don't drop GlobalAddress offset when handling extern_weak decls.
llvm-svn: 176258
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c7e0a04433
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@ -1864,10 +1864,16 @@ AArch64TargetLowering::LowerGlobalAddressELF(SDValue Op,
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DAG.getTargetConstantPool(GV, PtrVT, 0, 0,
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AArch64II::MO_LO12),
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DAG.getConstant(8, MVT::i32));
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return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), PoolAddr,
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MachinePointerInfo::getConstantPool(),
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/*isVolatile=*/ false, /*isNonTemporal=*/ true,
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/*isInvariant=*/ true, 8);
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SDValue GlobalAddr = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), PoolAddr,
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MachinePointerInfo::getConstantPool(),
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/*isVolatile=*/ false,
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/*isNonTemporal=*/ true,
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/*isInvariant=*/ true, 8);
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if (GN->getOffset() != 0)
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return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr,
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DAG.getConstant(GN->getOffset(), PtrVT));
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return GlobalAddr;
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}
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if (Alignment == 0) {
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@ -12,3 +12,16 @@ define i32()* @foo() {
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; CHECK: ldr x0, [{{x[0-9]+}}, #:lo12:.LCPI0_0]
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}
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@arr_var = extern_weak global [10 x i32]
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define i32* @bar() {
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%addr = getelementptr [10 x i32]* @arr_var, i32 0, i32 5
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; CHECK: .LCPI1_0:
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; CHECK-NEXT: .xword arr_var
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; CHECK: ldr [[BASE:x[0-9]+]], [{{x[0-9]+}}, #:lo12:.LCPI1_0]
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; CHECK: add x0, [[BASE]], #20
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ret i32* %addr
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}
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