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[X86] Allow base and index for gather instructions to appear in other order for Intel syntax. 

llvm-svn: 335500
This commit is contained in:
Craig Topper 2018-06-25 17:26:51 +00:00
parent 74282efee1
commit b9cb88a4b0
2 changed files with 16 additions and 0 deletions
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11
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -1883,6 +1883,17 @@ std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() {
(IndexReg == X86::ESP || IndexReg == X86::RSP))
std::swap(BaseReg, IndexReg);
// If BaseReg is a vector register and IndexReg is not, swap them unless
// Scale was specified in which case it would be an error.
if (Scale == 0 &&
!(X86MCRegisterClasses[X86::VR128XRegClassID].contains(IndexReg) ||
X86MCRegisterClasses[X86::VR256XRegClassID].contains(IndexReg) ||
X86MCRegisterClasses[X86::VR512RegClassID].contains(IndexReg)) &&
(X86MCRegisterClasses[X86::VR128XRegClassID].contains(BaseReg) ||
X86MCRegisterClasses[X86::VR256XRegClassID].contains(BaseReg) ||
X86MCRegisterClasses[X86::VR512RegClassID].contains(BaseReg)))
std::swap(BaseReg, IndexReg);
if (Scale != 0 &&
X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg))
return ErrorOperand(Start, "16-bit addresses cannot have a scale");

5
llvm/test/MC/X86/intel-syntax.s
View File

@ -897,3 +897,8 @@ lea rax, [rsp+rax]
lea eax, [eax+esp]
// CHECK: leal (%esp,%eax), %eax
lea eax, [esp+eax]
// CHECK: vpgatherdq %ymm2, (%rdi,%xmm1), %ymm0
vpgatherdq ymm0, [rdi+xmm1], ymm2
// CHECK: vpgatherdq %ymm2, (%rdi,%xmm1), %ymm0
vpgatherdq ymm0, [xmm1+rdi], ymm2