forked from OSchip/llvm-project
[AVR] Rewrite the function calling convention.
Summary: The previous version relied on the standard calling convention using std::reverse() to try to force the AVR ABI. But this only works for simple cases, it fails for example with aggregate types. This patch rewrites the calling convention with custom C++ code, that implements the ABI defined in https://gcc.gnu.org/wiki/avr-gcc. To do that it adds a few 16-bit pseudo registers for unaligned argument passing, such as R24R23. For example this function: define void @fun({ i8, i16 } %a) will pass %a.0 in R22 and %a.1 in R24R23. There are no instructions that can use these pseudo registers, so a new register class, DREGSMOVW, is defined to make them apart. Also the ArgCC_AVR_BUILTIN_DIV is no longer necessary, as it is identical to the C++ behavior (actually the clobber list is more strict for __div* functions, but that is currently unimplemented). Reviewers: dylanmckay Subscribers: Gaelan, Sh4rK, indirect, jwagen, efriedma, dsprenkels, hiraditya, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68524 Patch by Rodrigo Rivas Costa.
This commit is contained in:
Dylan McKay
parent
82a882db08
commit
b9c26a9cfe
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@ -6,21 +6,13 @@
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//
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//===----------------------------------------------------------------------===//
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// This describes the calling conventions for AVR architecture.
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// Normal functions use a special calling convention, solved in code.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// AVR Return Value Calling Convention
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//===----------------------------------------------------------------------===//
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def RetCC_AVR : CallingConv
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<[
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// i8 is returned in R24.
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CCIfType<[i8], CCAssignToReg<[R24]>>,
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// i16 are returned in R25:R24, R23:R22, R21:R20 and R19:R18.
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CCIfType<[i16], CCAssignToReg<[R25R24, R23R22, R21R20, R19R18]>>
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]>;
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// Special return value calling convention for runtime functions.
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def RetCC_AVR_BUILTIN : CallingConv
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<[
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@ -41,14 +33,6 @@ def ArgCC_AVR_Vararg : CallingConv
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CCAssignToStack<2, 1>
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]>;
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// Special argument calling convention for
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// division runtime functions.
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def ArgCC_AVR_BUILTIN_DIV : CallingConv
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<[
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CCIfType<[i8], CCAssignToReg<[R24,R22]>>,
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CCIfType<[i16], CCAssignToReg<[R25R24, R23R22]>>
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]>;
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//===----------------------------------------------------------------------===//
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// Callee-saved register lists.
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//===----------------------------------------------------------------------===//
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@ -14,6 +14,7 @@
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#include "AVRISelLowering.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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@ -881,172 +882,145 @@ bool AVRTargetLowering::isOffsetFoldingLegal(
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#include "AVRGenCallingConv.inc"
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/// For each argument in a function store the number of pieces it is composed
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/// of.
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static void parseFunctionArgs(const SmallVectorImpl<ISD::InputArg> &Ins,
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SmallVectorImpl<unsigned> &Out) {
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for (const ISD::InputArg &Arg : Ins) {
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if(Arg.PartOffset > 0) continue;
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unsigned Bytes = ((Arg.ArgVT.getSizeInBits()) + 7) / 8;
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/// Registers for calling conventions, ordered in reverse as required by ABI.
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/// Both arrays must be of the same length.
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static const MCPhysReg RegList8[] = {
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AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
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AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
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AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
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static const MCPhysReg RegList16[] = {
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AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22,
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AVR::R22R21, AVR::R21R20, AVR::R20R19, AVR::R19R18,
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AVR::R18R17, AVR::R17R16, AVR::R16R15, AVR::R15R14,
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AVR::R14R13, AVR::R13R12, AVR::R12R11, AVR::R11R10,
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AVR::R10R9, AVR::R9R8};
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Out.push_back((Bytes + 1) / 2);
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}
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}
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/// For external symbols there is no function prototype information so we
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/// have to rely directly on argument sizes.
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static void parseExternFuncCallArgs(const SmallVectorImpl<ISD::OutputArg> &In,
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SmallVectorImpl<unsigned> &Out) {
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for (unsigned i = 0, e = In.size(); i != e;) {
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unsigned Size = 0;
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unsigned Offset = 0;
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while ((i != e) && (In[i].PartOffset == Offset)) {
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Offset += In[i].VT.getStoreSize();
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++i;
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++Size;
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}
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Out.push_back(Size);
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}
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}
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static StringRef getFunctionName(TargetLowering::CallLoweringInfo &CLI) {
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SDValue Callee = CLI.Callee;
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if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee)) {
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return G->getSymbol();
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}
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if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
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return G->getGlobal()->getName();
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}
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llvm_unreachable("don't know how to get the name for this callee");
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}
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static_assert(array_lengthof(RegList8) == array_lengthof(RegList16),
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"8-bit and 16-bit register arrays must be of equal length");
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/// Analyze incoming and outgoing function arguments. We need custom C++ code
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/// to handle special constraints in the ABI like reversing the order of the
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/// pieces of splitted arguments. In addition, all pieces of a certain argument
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/// have to be passed either using registers or the stack but never mixing both.
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static void analyzeStandardArguments(TargetLowering::CallLoweringInfo *CLI,
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const Function *F, const DataLayout *TD,
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const SmallVectorImpl<ISD::OutputArg> *Outs,
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const SmallVectorImpl<ISD::InputArg> *Ins,
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CallingConv::ID CallConv,
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SmallVectorImpl<CCValAssign> &ArgLocs,
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CCState &CCInfo, bool IsCall, bool IsVarArg) {
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static const MCPhysReg RegList8[] = {AVR::R24, AVR::R22, AVR::R20,
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AVR::R18, AVR::R16, AVR::R14,
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AVR::R12, AVR::R10, AVR::R8};
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static const MCPhysReg RegList16[] = {AVR::R25R24, AVR::R23R22, AVR::R21R20,
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AVR::R19R18, AVR::R17R16, AVR::R15R14,
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AVR::R13R12, AVR::R11R10, AVR::R9R8};
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if (IsVarArg) {
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// Variadic functions do not need all the analysis below.
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if (IsCall) {
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CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_Vararg);
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} else {
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CCInfo.AnalyzeFormalArguments(*Ins, ArgCC_AVR_Vararg);
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/// to handle special constraints in the ABI.
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/// In addition, all pieces of a certain argument have to be passed either
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/// using registers or the stack but never mixing both.
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template <typename ArgT>
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static void
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analyzeArguments(TargetLowering::CallLoweringInfo *CLI, const Function *F,
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const DataLayout *TD, const SmallVectorImpl<ArgT> &Args,
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SmallVectorImpl<CCValAssign> &ArgLocs, CCState &CCInfo) {
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unsigned NumArgs = Args.size();
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// This is the index of the last used register, in RegList*.
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// -1 means R26 (R26 is never actually used in CC).
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int RegLastIdx = -1;
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// Once a value is passed to the stack it will always be used
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bool UseStack = false;
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for (unsigned i = 0; i != NumArgs;) {
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MVT VT = Args[i].VT;
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// We have to count the number of bytes for each function argument, that is
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// those Args with the same OrigArgIndex. This is important in case the
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// function takes an aggregate type.
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// Current argument will be between [i..j).
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unsigned ArgIndex = Args[i].OrigArgIndex;
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unsigned TotalBytes = VT.getStoreSize();
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unsigned j = i + 1;
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for (; j != NumArgs; ++j) {
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if (Args[j].OrigArgIndex != ArgIndex)
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break;
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TotalBytes += Args[j].VT.getStoreSize();
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}
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return;
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}
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// Round up to even number of bytes.
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TotalBytes = alignTo(TotalBytes, 2);
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// Skip zero sized arguments
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if (TotalBytes == 0)
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continue;
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// The index of the first register to be used
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unsigned RegIdx = RegLastIdx + TotalBytes;
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RegLastIdx = RegIdx;
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// If there are not enough registers, use the stack
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if (RegIdx >= array_lengthof(RegList8)) {
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UseStack = true;
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}
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for (; i != j; ++i) {
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MVT VT = Args[i].VT;
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// Fill in the Args array which will contain original argument sizes.
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SmallVector<unsigned, 8> Args;
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if (IsCall) {
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parseExternFuncCallArgs(*Outs, Args);
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} else {
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assert(F != nullptr && "function should not be null");
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parseFunctionArgs(*Ins, Args);
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}
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unsigned RegsLeft = array_lengthof(RegList8), ValNo = 0;
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// Variadic functions always use the stack.
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bool UsesStack = false;
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for (unsigned i = 0, pos = 0, e = Args.size(); i != e; ++i) {
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unsigned Size = Args[i];
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// If we have a zero-sized argument, don't attempt to lower it.
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// AVR-GCC does not support zero-sized arguments and so we need not
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// worry about ABI compatibility.
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if (Size == 0) continue;
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MVT LocVT = (IsCall) ? (*Outs)[pos].VT : (*Ins)[pos].VT;
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// If we have plenty of regs to pass the whole argument do it.
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if (!UsesStack && (Size <= RegsLeft)) {
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const MCPhysReg *RegList = (LocVT == MVT::i16) ? RegList16 : RegList8;
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for (unsigned j = 0; j != Size; ++j) {
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unsigned Reg = CCInfo.AllocateReg(
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ArrayRef<MCPhysReg>(RegList, array_lengthof(RegList8)));
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if (UseStack) {
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auto evt = EVT(VT).getTypeForEVT(CCInfo.getContext());
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unsigned Offset = CCInfo.AllocateStack(TD->getTypeAllocSize(evt),
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TD->getABITypeAlign(evt));
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CCInfo.addLoc(
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CCValAssign::getReg(ValNo++, LocVT, Reg, LocVT, CCValAssign::Full));
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--RegsLeft;
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}
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// Reverse the order of the pieces to agree with the "big endian" format
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// required in the calling convention ABI.
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std::reverse(ArgLocs.begin() + pos, ArgLocs.begin() + pos + Size);
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} else {
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// Pass the rest of arguments using the stack.
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UsesStack = true;
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for (unsigned j = 0; j != Size; ++j) {
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unsigned Offset = CCInfo.AllocateStack(
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TD->getTypeAllocSize(EVT(LocVT).getTypeForEVT(CCInfo.getContext())),
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TD->getABITypeAlign(EVT(LocVT).getTypeForEVT(CCInfo.getContext())));
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CCInfo.addLoc(CCValAssign::getMem(ValNo++, LocVT, Offset, LocVT,
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CCValAssign::Full));
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CCValAssign::getMem(i, VT, Offset, VT, CCValAssign::Full));
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} else {
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unsigned Reg;
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if (VT == MVT::i8) {
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Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
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} else if (VT == MVT::i16) {
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Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
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} else {
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llvm_unreachable(
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"calling convention can only manage i8 and i16 types");
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}
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assert(Reg && "register not available in calling convention");
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CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
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// Registers inside a particular argument are sorted in increasing order
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// (remember the array is reversed).
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RegIdx -= VT.getStoreSize();
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}
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}
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pos += Size;
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}
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}
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static void analyzeBuiltinArguments(TargetLowering::CallLoweringInfo &CLI,
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const Function *F, const DataLayout *TD,
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const SmallVectorImpl<ISD::OutputArg> *Outs,
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const SmallVectorImpl<ISD::InputArg> *Ins,
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CallingConv::ID CallConv,
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SmallVectorImpl<CCValAssign> &ArgLocs,
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CCState &CCInfo, bool IsCall, bool IsVarArg) {
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StringRef FuncName = getFunctionName(CLI);
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/// Count the total number of bytes needed to pass or return these arguments.
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template <typename ArgT>
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static unsigned getTotalArgumentsSizeInBytes(const SmallVectorImpl<ArgT> &Args) {
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unsigned TotalBytes = 0;
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if (FuncName.startswith("__udivmod") || FuncName.startswith("__divmod")) {
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CCInfo.AnalyzeCallOperands(*Outs, ArgCC_AVR_BUILTIN_DIV);
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for (const ArgT& Arg : Args) {
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TotalBytes += Arg.VT.getStoreSize();
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}
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return TotalBytes;
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}
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/// Analyze incoming and outgoing value of returning from a function.
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/// The algorithm is similar to analyzeArguments, but there can only be
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/// one value, possibly an aggregate, and it is limited to 8 bytes.
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template <typename ArgT>
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static void analyzeReturnValues(const SmallVectorImpl<ArgT> &Args,
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CCState &CCInfo) {
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unsigned NumArgs = Args.size();
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unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args);
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// CanLowerReturn() guarantees this assertion.
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assert(TotalBytes <= 8 && "return values greater than 8 bytes cannot be lowered");
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// GCC-ABI says that the size is rounded up to the next even number,
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// but actually once it is more than 4 it will always round up to 8.
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if (TotalBytes > 4) {
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TotalBytes = 8;
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} else {
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analyzeStandardArguments(&CLI, F, TD, Outs, Ins,
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CallConv, ArgLocs, CCInfo,
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IsCall, IsVarArg);
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TotalBytes = alignTo(TotalBytes, 2);
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}
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}
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static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI,
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const Function *F, const DataLayout *TD,
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const SmallVectorImpl<ISD::OutputArg> *Outs,
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const SmallVectorImpl<ISD::InputArg> *Ins,
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CallingConv::ID CallConv,
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SmallVectorImpl<CCValAssign> &ArgLocs,
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CCState &CCInfo, bool IsCall, bool IsVarArg) {
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switch (CallConv) {
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case CallingConv::AVR_BUILTIN: {
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analyzeBuiltinArguments(*CLI, F, TD, Outs, Ins,
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CallConv, ArgLocs, CCInfo,
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IsCall, IsVarArg);
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return;
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}
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default: {
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analyzeStandardArguments(CLI, F, TD, Outs, Ins,
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CallConv, ArgLocs, CCInfo,
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IsCall, IsVarArg);
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return;
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// The index of the first register to use.
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int RegIdx = TotalBytes - 1;
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for (unsigned i = 0; i != NumArgs; ++i) {
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MVT VT = Args[i].VT;
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unsigned Reg;
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if (VT == MVT::i8) {
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Reg = CCInfo.AllocateReg(RegList8[RegIdx]);
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} else if (VT == MVT::i16) {
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Reg = CCInfo.AllocateReg(RegList16[RegIdx]);
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} else {
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llvm_unreachable("calling convention can only manage i8 and i16 types");
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}
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assert(Reg && "register not available in calling convention");
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CCInfo.addLoc(CCValAssign::getReg(i, VT, Reg, VT, CCValAssign::Full));
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// Registers sort in increasing order
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RegIdx -= VT.getStoreSize();
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}
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}
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SDValue AVRTargetLowering::LowerFormalArguments(
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SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
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SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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auto DL = DAG.getDataLayout();
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@ -1056,8 +1030,12 @@ SDValue AVRTargetLowering::LowerFormalArguments(
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CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
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*DAG.getContext());
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analyzeArguments(nullptr, &MF.getFunction(), &DL, 0, &Ins, CallConv, ArgLocs, CCInfo,
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false, isVarArg);
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// Variadic functions do not need all the analysis below.
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if (isVarArg) {
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CCInfo.AnalyzeFormalArguments(Ins, ArgCC_AVR_Vararg);
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} else {
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analyzeArguments(nullptr, &MF.getFunction(), &DL, Ins, ArgLocs, CCInfo);
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}
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SDValue ArgValue;
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for (CCValAssign &VA : ArgLocs) {
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@ -1178,8 +1156,12 @@ SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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getPointerTy(DAG.getDataLayout()));
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}
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analyzeArguments(&CLI, F, &DAG.getDataLayout(), &Outs, 0, CallConv, ArgLocs, CCInfo,
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true, isVarArg);
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// Variadic functions do not need all the analysis below.
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if (isVarArg) {
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CCInfo.AnalyzeCallOperands(Outs, ArgCC_AVR_Vararg);
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} else {
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analyzeArguments(&CLI, F, &DAG.getDataLayout(), Outs, ArgLocs, CCInfo);
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}
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = CCInfo.getNextStackOffset();
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@ -1316,13 +1298,10 @@ SDValue AVRTargetLowering::LowerCallResult(
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*DAG.getContext());
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// Handle runtime calling convs.
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auto CCFunction = CCAssignFnForReturn(CallConv);
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CCInfo.AnalyzeCallResult(Ins, CCFunction);
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if (CallConv != CallingConv::AVR_BUILTIN && RVLocs.size() > 1) {
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// Reverse splitted return values to get the "big endian" format required
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// to agree with the calling convention ABI.
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std::reverse(RVLocs.begin(), RVLocs.end());
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if (CallConv == CallingConv::AVR_BUILTIN) {
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CCInfo.AnalyzeCallResult(Ins, RetCC_AVR_BUILTIN);
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} else {
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analyzeReturnValues(Ins, CCInfo);
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}
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// Copy all of the result registers out of their specified physreg.
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@ -1341,26 +1320,17 @@ SDValue AVRTargetLowering::LowerCallResult(
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// Return Value Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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CCAssignFn *AVRTargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const {
|
||||
switch (CC) {
|
||||
case CallingConv::AVR_BUILTIN:
|
||||
return RetCC_AVR_BUILTIN;
|
||||
default:
|
||||
return RetCC_AVR;
|
||||
bool AVRTargetLowering::CanLowerReturn(
|
||||
CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
|
||||
if (CallConv == CallingConv::AVR_BUILTIN) {
|
||||
SmallVector<CCValAssign, 16> RVLocs;
|
||||
CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
|
||||
return CCInfo.CheckReturn(Outs, RetCC_AVR_BUILTIN);
|
||||
}
|
||||
}
|
||||
|
||||
bool
|
||||
AVRTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
|
||||
MachineFunction &MF, bool isVarArg,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
LLVMContext &Context) const
|
||||
{
|
||||
SmallVector<CCValAssign, 16> RVLocs;
|
||||
CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
|
||||
|
||||
auto CCFunction = CCAssignFnForReturn(CallConv);
|
||||
return CCInfo.CheckReturn(Outs, CCFunction);
|
||||
unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs);
|
||||
return TotalBytes <= 8;
|
||||
}
|
||||
|
||||
SDValue
|
||||
|
|
@ -1376,25 +1346,19 @@ AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
|
|||
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
|
||||
*DAG.getContext());
|
||||
|
||||
// Analyze return values.
|
||||
auto CCFunction = CCAssignFnForReturn(CallConv);
|
||||
CCInfo.AnalyzeReturn(Outs, CCFunction);
|
||||
|
||||
// If this is the first return lowered for this function, add the regs to
|
||||
// the liveout set for the function.
|
||||
MachineFunction &MF = DAG.getMachineFunction();
|
||||
unsigned e = RVLocs.size();
|
||||
|
||||
// Reverse splitted return values to get the "big endian" format required
|
||||
// to agree with the calling convention ABI.
|
||||
if (e > 1) {
|
||||
std::reverse(RVLocs.begin(), RVLocs.end());
|
||||
// Analyze return values.
|
||||
if (CallConv == CallingConv::AVR_BUILTIN) {
|
||||
CCInfo.AnalyzeReturn(Outs, RetCC_AVR_BUILTIN);
|
||||
} else {
|
||||
analyzeReturnValues(Outs, CCInfo);
|
||||
}
|
||||
|
||||
SDValue Flag;
|
||||
SmallVector<SDValue, 4> RetOps(1, Chain);
|
||||
// Copy the result values into the output registers.
|
||||
for (unsigned i = 0; i != e; ++i) {
|
||||
for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
|
||||
CCValAssign &VA = RVLocs[i];
|
||||
assert(VA.isRegLoc() && "Can only return in registers!");
|
||||
|
||||
|
|
|
|||
|
|
@ -146,10 +146,8 @@ private:
|
|||
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
||||
CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const;
|
||||
|
||||
bool CanLowerReturn(CallingConv::ID CallConv,
|
||||
MachineFunction &MF, bool isVarArg,
|
||||
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
|
||||
bool isVarArg,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
LLVMContext &Context) const override;
|
||||
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
|
|||
|
||||
// Not all AVR devices support the 16-bit `MOVW` instruction.
|
||||
if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) {
|
||||
if (STI.hasMOVW()) {
|
||||
if (STI.hasMOVW() && AVR::DREGSMOVWRegClass.contains(DestReg, SrcReg)) {
|
||||
BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg)
|
||||
.addReg(SrcReg, getKillRegState(KillSrc));
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -103,6 +103,17 @@ CoveredBySubRegs = 1 in
|
|||
def R5R4 : AVRReg<4, "r5:r4", [R4, R5]>, DwarfRegNum<[4]>;
|
||||
def R3R2 : AVRReg<2, "r3:r2", [R2, R3]>, DwarfRegNum<[2]>;
|
||||
def R1R0 : AVRReg<0, "r1:r0", [R0, R1]>, DwarfRegNum<[0]>;
|
||||
|
||||
// Pseudo registers for unaligned i16
|
||||
def R26R25 : AVRReg<25, "r26:r25", [R25, R26]>, DwarfRegNum<[25]>;
|
||||
def R24R23 : AVRReg<23, "r24:r23", [R23, R24]>, DwarfRegNum<[23]>;
|
||||
def R22R21 : AVRReg<21, "r22:r21", [R21, R22]>, DwarfRegNum<[21]>;
|
||||
def R20R19 : AVRReg<19, "r20:r19", [R19, R20]>, DwarfRegNum<[19]>;
|
||||
def R18R17 : AVRReg<17, "r18:r17", [R17, R18]>, DwarfRegNum<[17]>;
|
||||
def R16R15 : AVRReg<15, "r16:r15", [R15, R16]>, DwarfRegNum<[15]>;
|
||||
def R14R13 : AVRReg<13, "r14:r13", [R13, R14]>, DwarfRegNum<[13]>;
|
||||
def R12R11 : AVRReg<11, "r12:r11", [R11, R12]>, DwarfRegNum<[11]>;
|
||||
def R10R9 : AVRReg<9, "r10:r9", [R9, R10]>, DwarfRegNum<[9]>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -146,6 +157,22 @@ def LD8lo : RegisterClass<"AVR", [i8], 8,
|
|||
|
||||
// Main 16-bit pair register class.
|
||||
def DREGS : RegisterClass<"AVR", [i16], 8,
|
||||
(
|
||||
// Return value and arguments.
|
||||
add R25R24, R19R18, R21R20, R23R22,
|
||||
// Scratch registers.
|
||||
R31R30, R27R26,
|
||||
// Callee saved registers.
|
||||
R29R28, R17R16, R15R14, R13R12, R11R10,
|
||||
R9R8, R7R6, R5R4, R3R2, R1R0,
|
||||
// Pseudo regs for unaligned 16-bits
|
||||
R26R25, R24R23, R22R21,
|
||||
R20R19, R18R17, R16R15,
|
||||
R14R13, R12R11, R10R9
|
||||
)>;
|
||||
|
||||
// 16-bit pair register class for movw
|
||||
def DREGSMOVW : RegisterClass<"AVR", [i16], 8,
|
||||
(
|
||||
// Return value and arguments.
|
||||
add R25R24, R19R18, R21R20, R23R22,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,84 @@
|
|||
; RUN: llc < %s -march=avr | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: ret_void_args_struct_i8_i32
|
||||
define void @ret_void_args_struct_i8_i32({ i8, i32 } %a) {
|
||||
start:
|
||||
; CHECK: sts 4, r20
|
||||
%0 = extractvalue { i8, i32 } %a, 0
|
||||
store volatile i8 %0, i8* inttoptr (i64 4 to i8*)
|
||||
|
||||
; CHECK-NEXT: sts 8, r24
|
||||
; CHECK-NEXT: sts 7, r23
|
||||
; CHECK-NEXT: sts 6, r22
|
||||
; CHECK-NEXT: sts 5, r21
|
||||
%1 = extractvalue { i8, i32 } %a, 1
|
||||
store volatile i32 %1, i32* inttoptr (i64 5 to i32*)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: ret_void_args_struct_i8_i8_i8_i8
|
||||
define void @ret_void_args_struct_i8_i8_i8_i8({ i8, i8, i8, i8 } %a) {
|
||||
start:
|
||||
; CHECK: sts 4, r22
|
||||
%0 = extractvalue { i8, i8, i8, i8 } %a, 0
|
||||
store volatile i8 %0, i8* inttoptr (i64 4 to i8*)
|
||||
; CHECK-NEXT: sts 5, r23
|
||||
%1 = extractvalue { i8, i8, i8, i8 } %a, 1
|
||||
store volatile i8 %1, i8* inttoptr (i64 5 to i8*)
|
||||
; CHECK-NEXT: sts 6, r24
|
||||
%2 = extractvalue { i8, i8, i8, i8 } %a, 2
|
||||
store volatile i8 %2, i8* inttoptr (i64 6 to i8*)
|
||||
; CHECK-NEXT: sts 7, r25
|
||||
%3 = extractvalue { i8, i8, i8, i8 } %a, 3
|
||||
store volatile i8 %3, i8* inttoptr (i64 7 to i8*)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: ret_void_args_struct_i32_16_i8
|
||||
define void @ret_void_args_struct_i32_16_i8({ i32, i16, i8} %a) {
|
||||
start:
|
||||
; CHECK: sts 7, r21
|
||||
; CHECK-NEXT: sts 6, r20
|
||||
; CHECK-NEXT: sts 5, r19
|
||||
; CHECK-NEXT: sts 4, r18
|
||||
%0 = extractvalue { i32, i16, i8 } %a, 0
|
||||
store volatile i32 %0, i32* inttoptr (i64 4 to i32*)
|
||||
|
||||
; CHECK-NEXT: sts 5, r23
|
||||
; CHECK-NEXT: sts 4, r22
|
||||
%1 = extractvalue { i32, i16, i8 } %a, 1
|
||||
store volatile i16 %1, i16* inttoptr (i64 4 to i16*)
|
||||
|
||||
; CHECK-NEXT: sts 4, r24
|
||||
%2 = extractvalue { i32, i16, i8 } %a, 2
|
||||
store volatile i8 %2, i8* inttoptr (i64 4 to i8*)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: ret_void_args_struct_i8_i32_struct_i32_i8
|
||||
define void @ret_void_args_struct_i8_i32_struct_i32_i8({ i8, i32 } %a, { i32, i8 } %b) {
|
||||
start:
|
||||
; CHECK: sts 4, r20
|
||||
%0 = extractvalue { i8, i32 } %a, 0
|
||||
store volatile i8 %0, i8* inttoptr (i64 4 to i8*)
|
||||
|
||||
; CHECK-NEXT: sts 8, r24
|
||||
; CHECK-NEXT: sts 7, r23
|
||||
; CHECK-NEXT: sts 6, r22
|
||||
; CHECK-NEXT: sts 5, r21
|
||||
%1 = extractvalue { i8, i32 } %a, 1
|
||||
store volatile i32 %1, i32* inttoptr (i64 5 to i32*)
|
||||
|
||||
; CHECK-NEXT: sts 9, r17
|
||||
; CHECK-NEXT: sts 8, r16
|
||||
; CHECK-NEXT: sts 7, r15
|
||||
; CHECK-NEXT: sts 6, r14
|
||||
%2 = extractvalue { i32, i8 } %b, 0
|
||||
store volatile i32 %2, i32* inttoptr (i64 6 to i32*)
|
||||
|
||||
; CHECK-NEXT: sts 7, r18
|
||||
%3 = extractvalue { i32, i8 } %b, 1
|
||||
store volatile i8 %3, i8* inttoptr (i64 7 to i8*)
|
||||
ret void
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
; RUN: llc < %s -march=avr | FileCheck %s
|
||||
|
||||
declare void @ret_void_args_i8(i8 %a)
|
||||
declare void @ret_void_args_i8_i32(i8 %a, i32 %b)
|
||||
declare void @ret_void_args_i8_i8_i8_i8(i8 %a, i8 %b, i8 %c, i8 %d)
|
||||
declare void @ret_void_args_i32_i16_i8(i32 %a, i16 %b, i8 %c)
|
||||
declare void @ret_void_args_i64(i64 %a)
|
||||
declare void @ret_void_args_i64_i64(i64 %a, i64 %b)
|
||||
declare void @ret_void_args_i64_i64_i16(i64 %a, i64 %b, i16 %c)
|
||||
|
||||
; CHECK-LABEL: call_void_args_i8
|
||||
define void @call_void_args_i8() {
|
||||
; CHECK: ldi r24, 64
|
||||
call void @ret_void_args_i8 (i8 64)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: call_void_args_i8_i32
|
||||
define void @call_void_args_i8_i32() {
|
||||
; CHECK: ldi r20, 4
|
||||
; CHECK-NEXT: ldi r21, 3
|
||||
; CHECK-NEXT: ldi r22, 2
|
||||
; CHECK-NEXT: ldi r23, 1
|
||||
; CHECK-NEXT: ldi r24, 64
|
||||
call void @ret_void_args_i8_i32 (i8 64, i32 16909060)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: call_void_args_i8_i8_i8_i8
|
||||
define void @call_void_args_i8_i8_i8_i8() {
|
||||
; CHECK: ldi r24, 1
|
||||
; CHECK-NEXT: ldi r22, 2
|
||||
; CHECK-NEXT: ldi r20, 3
|
||||
; CHECK-NEXT: ldi r18, 4
|
||||
call void @ret_void_args_i8_i8_i8_i8(i8 1, i8 2, i8 3, i8 4)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: call_void_args_i32_i16_i8
|
||||
define void @call_void_args_i32_i16_i8() {
|
||||
; CHECK: ldi r22, 4
|
||||
; CHECK-NEXT: ldi r23, 3
|
||||
; CHECK-NEXT: ldi r24, 2
|
||||
; CHECK-NEXT: ldi r25, 1
|
||||
; CHECK-NEXT: ldi r20, 1
|
||||
; CHECK-NEXT: ldi r21, 4
|
||||
; CHECK-NEXT: ldi r18, 64
|
||||
call void @ret_void_args_i32_i16_i8(i32 16909060, i16 1025, i8 64)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: call_void_args_i64
|
||||
define void @call_void_args_i64() {
|
||||
; CHECK: ldi r18, 8
|
||||
; CHECK-NEXT: ldi r19, 7
|
||||
; CHECK-NEXT: ldi r20, 6
|
||||
; CHECK-NEXT: ldi r21, 5
|
||||
; CHECK-NEXT: ldi r22, 4
|
||||
; CHECK-NEXT: ldi r23, 3
|
||||
; CHECK-NEXT: ldi r24, 2
|
||||
; CHECK-NEXT: ldi r25, 1
|
||||
call void @ret_void_args_i64(i64 72623859790382856)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: call_void_args_i64_i64
|
||||
define void @call_void_args_i64_i64() {
|
||||
; CHECK: ldi r18, 8
|
||||
; CHECK-NEXT: ldi r19, 7
|
||||
; CHECK-NEXT: ldi r20, 6
|
||||
; CHECK-NEXT: ldi r21, 5
|
||||
; CHECK-NEXT: ldi r22, 4
|
||||
; CHECK-NEXT: ldi r23, 3
|
||||
; CHECK-NEXT: ldi r24, 2
|
||||
; CHECK-NEXT: ldi r25, 1
|
||||
; the second arg is in r10:r17, but unordered
|
||||
; CHECK: r17,
|
||||
; CHECK: r10,
|
||||
call void @ret_void_args_i64_i64(i64 72623859790382856, i64 651345242494996224)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: call_void_args_i64_i64_i16
|
||||
define void @call_void_args_i64_i64_i16() {
|
||||
; CHECK: r8,
|
||||
; CHECK: r9,
|
||||
call void @ret_void_args_i64_i64_i16(i64 72623859790382856, i64 651345242494996224, i16 5655)
|
||||
ret void
|
||||
}
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
; RUN: llc < %s -march=avr | FileCheck %s
|
||||
|
||||
declare void @ret_void_args_struct_i8_i32({ i8, i32 } %a)
|
||||
declare void @ret_void_args_struct_i8_i8_i8_i8({ i8, i8, i8, i8 } %a)
|
||||
declare void @ret_void_args_struct_i32_i16_i8({ i32, i16, i8} %a)
|
||||
declare void @ret_void_args_struct_i8_i32_struct_i32_i8({ i8, i32 } %a, { i32, i8 } %b)
|
||||
|
||||
; CHECK-LABEL: call_void_args_struct_i8_i32
|
||||
define void @call_void_args_struct_i8_i32() {
|
||||
; CHECK: ldi r20, 64
|
||||
; CHECK-NEXT: r21,
|
||||
; CHECK-NEXT: r22,
|
||||
; CHECK-NEXT: r23,
|
||||
; CHECK-NEXT: r24,
|
||||
call void @ret_void_args_struct_i8_i32({ i8, i32 } { i8 64, i32 16909060 })
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @call_void_args_struct_i8_i8_i8_i8
|
||||
define void @call_void_args_struct_i8_i8_i8_i8() {
|
||||
; CHECK: ldi r22, 1
|
||||
; CHECK-NEXT: ldi r23, 2
|
||||
; CHECK-NEXT: ldi r24, 3
|
||||
; CHECK-NEXT: ldi r25, 4
|
||||
call void @ret_void_args_struct_i8_i8_i8_i8({ i8, i8, i8, i8 } { i8 1, i8 2, i8 3, i8 4 })
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @call_void_args_struct_i32_i16_i8
|
||||
define void @call_void_args_struct_i32_i16_i8() {
|
||||
; CHECK: ldi r18, 4
|
||||
; CHECK-NEXT: ldi r19, 3
|
||||
; CHECK-NEXT: ldi r20, 2
|
||||
; CHECK-NEXT: ldi r21, 1
|
||||
; CHECK-NEXT: ldi r22, 23
|
||||
; CHECK-NEXT: ldi r23, 22
|
||||
; CHECK-NEXT: ldi r24, 64
|
||||
call void @ret_void_args_struct_i32_i16_i8({ i32, i16, i8 } { i32 16909060, i16 5655, i8 64 })
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @call_void_args_struct_i8_i32_struct_i32_i8
|
||||
define void @call_void_args_struct_i8_i32_struct_i32_i8() {
|
||||
; CHECK: ldi r20, 64
|
||||
; CHECK: ldi r18, 65
|
||||
call void @ret_void_args_struct_i8_i32_struct_i32_i8({ i8, i32 } { i8 64, i32 16909060 }, { i32, i8 } { i32 287454020, i8 65 })
|
||||
ret void
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
; RUN: llc < %s -march=avr | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: ret_struct_i8_i16_i8
|
||||
define { i8, i16, i8 } @ret_struct_i8_i16_i8() {
|
||||
start:
|
||||
; for some reason the i16 is loaded to r24:r25
|
||||
; and then moved to r23:r24
|
||||
; CHECK: ldi r22, 64
|
||||
; CHECK-NEXT: r23,
|
||||
; CHECK-NEXT: r24,
|
||||
; CHECK-NEXT: r25, 11
|
||||
%0 = insertvalue {i8, i16, i8} undef, i8 64, 0
|
||||
%1 = insertvalue {i8, i16, i8} %0, i16 1024, 1
|
||||
%2 = insertvalue {i8, i16, i8} %1, i8 11, 2
|
||||
ret {i8, i16, i8} %2
|
||||
}
|
||||
|
||||
; CHECK-LABEL: ret_struct_i32_i16
|
||||
define { i32, i16 } @ret_struct_i32_i16() {
|
||||
start:
|
||||
; CHECK: ldi r18, 4
|
||||
; CHECK-NEXT: ldi r19, 3
|
||||
; CHECK-NEXT: ldi r20, 2
|
||||
; CHECK-NEXT: ldi r21, 1
|
||||
; CHECK-NEXT: ldi r22, 0
|
||||
; CHECK-NEXT: ldi r23, 8
|
||||
%0 = insertvalue { i32, i16 } undef, i32 16909060, 0
|
||||
%1 = insertvalue { i32, i16 } %0, i16 2048, 1
|
||||
ret { i32, i16} %1
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue