forked from OSchip/llvm-project
Add missing mayLoad / mayStore flags to instruction definitions without patterns,
which fixes all of the CodeGen/MBlaze verifier failures. llvm-svn: 131595
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@ -245,20 +245,25 @@ class PatCmp<bits<6> op, bits<11> flags, string instr_asm> :
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Memory Access Instructions
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// Memory Access Instructions
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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let mayLoad = 1 in {
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class LoadM<bits<6> op, bits<11> flags, string instr_asm> :
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class LoadM<bits<6> op, bits<11> flags, string instr_asm> :
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TA<op, flags, (outs GPR:$dst), (ins memrr:$addr),
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TA<op, flags, (outs GPR:$dst), (ins memrr:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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!strconcat(instr_asm, " $dst, $addr"),
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[], IIC_MEMl>;
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[], IIC_MEMl>;
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}
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class LoadMI<bits<6> op, string instr_asm, PatFrag OpNode> :
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class LoadMI<bits<6> op, string instr_asm, PatFrag OpNode> :
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TB<op, (outs GPR:$dst), (ins memri:$addr),
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TB<op, (outs GPR:$dst), (ins memri:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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!strconcat(instr_asm, " $dst, $addr"),
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[(set (i32 GPR:$dst), (OpNode iaddr:$addr))], IIC_MEMl>;
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[(set (i32 GPR:$dst), (OpNode iaddr:$addr))], IIC_MEMl>;
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let mayStore = 1 in {
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class StoreM<bits<6> op, bits<11> flags, string instr_asm> :
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class StoreM<bits<6> op, bits<11> flags, string instr_asm> :
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TA<op, flags, (outs), (ins GPR:$dst, memrr:$addr),
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TA<op, flags, (outs), (ins GPR:$dst, memrr:$addr),
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!strconcat(instr_asm, " $dst, $addr"),
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!strconcat(instr_asm, " $dst, $addr"),
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[], IIC_MEMs>;
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[], IIC_MEMs>;
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}
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class StoreMI<bits<6> op, string instr_asm, PatFrag OpNode> :
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class StoreMI<bits<6> op, string instr_asm, PatFrag OpNode> :
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TB<op, (outs), (ins GPR:$dst, memri:$addr),
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TB<op, (outs), (ins GPR:$dst, memri:$addr),
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