forked from OSchip/llvm-project
Pre-commit PowerPC case for zero/inf fpclassify
This commit is contained in:
Qiu Chaofan
parent
097ce76165
commit
b9be5a6823
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s \
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; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=P8
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s \
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; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=P9
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define zeroext i1 @abs_isinff(float %x) {
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; P8-LABEL: abs_isinff:
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; P8: # %bb.0: # %entry
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; P8-NEXT: xsabsdp 0, 1
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; P8-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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; P8-NEXT: li 4, 1
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; P8-NEXT: lfs 1, .LCPI0_0@toc@l(3)
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; P8-NEXT: li 3, 0
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; P8-NEXT: fcmpu 0, 0, 1
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; P8-NEXT: iseleq 3, 4, 3
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; P8-NEXT: blr
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;
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; P9-LABEL: abs_isinff:
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; P9: # %bb.0: # %entry
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; P9-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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; P9-NEXT: xsabsdp 0, 1
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; P9-NEXT: li 4, 1
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; P9-NEXT: lfs 1, .LCPI0_0@toc@l(3)
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; P9-NEXT: li 3, 0
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; P9-NEXT: fcmpu 0, 0, 1
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; P9-NEXT: iseleq 3, 4, 3
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; P9-NEXT: blr
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entry:
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%0 = tail call float @llvm.fabs.f32(float %x)
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%cmpinf = fcmp oeq float %0, 0x7FF0000000000000
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ret i1 %cmpinf
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}
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define zeroext i1 @abs_isinf(double %x) {
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; P8-LABEL: abs_isinf:
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; P8: # %bb.0: # %entry
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; P8-NEXT: xsabsdp 0, 1
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; P8-NEXT: addis 3, 2, .LCPI1_0@toc@ha
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; P8-NEXT: li 4, 1
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; P8-NEXT: lfs 1, .LCPI1_0@toc@l(3)
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; P8-NEXT: li 3, 0
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; P8-NEXT: fcmpu 0, 0, 1
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; P8-NEXT: iseleq 3, 4, 3
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; P8-NEXT: blr
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;
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; P9-LABEL: abs_isinf:
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; P9: # %bb.0: # %entry
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; P9-NEXT: addis 3, 2, .LCPI1_0@toc@ha
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; P9-NEXT: xsabsdp 0, 1
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; P9-NEXT: li 4, 1
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; P9-NEXT: lfs 1, .LCPI1_0@toc@l(3)
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; P9-NEXT: li 3, 0
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; P9-NEXT: fcmpu 0, 0, 1
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; P9-NEXT: iseleq 3, 4, 3
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; P9-NEXT: blr
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entry:
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%0 = tail call double @llvm.fabs.f64(double %x)
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%cmpinf = fcmp oeq double %0, 0x7FF0000000000000
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ret i1 %cmpinf
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}
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define zeroext i1 @abs_isinfq(fp128 %x) {
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; P8-LABEL: abs_isinfq:
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; P8: # %bb.0: # %entry
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; P8-NEXT: mflr 0
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; P8-NEXT: stdu 1, -48(1)
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; P8-NEXT: std 0, 64(1)
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; P8-NEXT: .cfi_def_cfa_offset 48
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; P8-NEXT: .cfi_offset lr, 16
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; P8-NEXT: xxswapd 0, 34
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; P8-NEXT: addi 3, 1, 32
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; P8-NEXT: stxvd2x 0, 0, 3
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; P8-NEXT: lbz 4, 47(1)
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; P8-NEXT: clrlwi 4, 4, 25
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; P8-NEXT: stb 4, 47(1)
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; P8-NEXT: lxvd2x 0, 0, 3
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; P8-NEXT: addis 3, 2, .LCPI2_0@toc@ha
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; P8-NEXT: addi 3, 3, .LCPI2_0@toc@l
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; P8-NEXT: xxswapd 34, 0
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; P8-NEXT: lxvd2x 0, 0, 3
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; P8-NEXT: xxswapd 35, 0
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; P8-NEXT: bl __eqkf2
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; P8-NEXT: nop
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; P8-NEXT: cntlzw 3, 3
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; P8-NEXT: srwi 3, 3, 5
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; P8-NEXT: addi 1, 1, 48
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; P8-NEXT: ld 0, 16(1)
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; P8-NEXT: mtlr 0
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; P8-NEXT: blr
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;
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; P9-LABEL: abs_isinfq:
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; P9: # %bb.0: # %entry
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; P9-NEXT: addis 3, 2, .LCPI2_0@toc@ha
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; P9-NEXT: xsabsqp 2, 2
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; P9-NEXT: li 4, 1
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; P9-NEXT: addi 3, 3, .LCPI2_0@toc@l
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; P9-NEXT: lxv 35, 0(3)
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; P9-NEXT: li 3, 0
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; P9-NEXT: xscmpuqp 0, 2, 3
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; P9-NEXT: iseleq 3, 4, 3
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; P9-NEXT: blr
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entry:
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%0 = tail call fp128 @llvm.fabs.f128(fp128 %x)
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%cmpinf = fcmp oeq fp128 %0, 0xL00000000000000007FFF000000000000
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ret i1 %cmpinf
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}
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define <4 x i1> @abs_isinfv4f32(<4 x float> %x) {
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; P8-LABEL: abs_isinfv4f32:
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; P8: # %bb.0: # %entry
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; P8-NEXT: addis 3, 2, .LCPI3_0@toc@ha
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; P8-NEXT: xvabssp 0, 34
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; P8-NEXT: addi 3, 3, .LCPI3_0@toc@l
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; P8-NEXT: lxvd2x 1, 0, 3
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; P8-NEXT: xxswapd 1, 1
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; P8-NEXT: xvcmpeqsp 34, 0, 1
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; P8-NEXT: blr
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;
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; P9-LABEL: abs_isinfv4f32:
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; P9: # %bb.0: # %entry
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; P9-NEXT: addis 3, 2, .LCPI3_0@toc@ha
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; P9-NEXT: xvabssp 0, 34
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; P9-NEXT: addi 3, 3, .LCPI3_0@toc@l
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; P9-NEXT: lxv 1, 0(3)
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; P9-NEXT: xvcmpeqsp 34, 0, 1
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; P9-NEXT: blr
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entry:
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%0 = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %x)
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%cmpinf = fcmp oeq <4 x float> %0, <float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000, float 0x7FF0000000000000>
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ret <4 x i1> %cmpinf
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}
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define <2 x i1> @abs_isinfv2f64(<2 x double> %x) {
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; P8-LABEL: abs_isinfv2f64:
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; P8: # %bb.0: # %entry
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; P8-NEXT: addis 3, 2, .LCPI4_0@toc@ha
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; P8-NEXT: xvabsdp 0, 34
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; P8-NEXT: addi 3, 3, .LCPI4_0@toc@l
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; P8-NEXT: lxvd2x 1, 0, 3
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; P8-NEXT: xxswapd 1, 1
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; P8-NEXT: xvcmpeqdp 34, 0, 1
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; P8-NEXT: blr
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;
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; P9-LABEL: abs_isinfv2f64:
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; P9: # %bb.0: # %entry
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; P9-NEXT: addis 3, 2, .LCPI4_0@toc@ha
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; P9-NEXT: xvabsdp 0, 34
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; P9-NEXT: addi 3, 3, .LCPI4_0@toc@l
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; P9-NEXT: lxv 1, 0(3)
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; P9-NEXT: xvcmpeqdp 34, 0, 1
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; P9-NEXT: blr
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entry:
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%0 = tail call <2 x double> @llvm.fabs.v2f64(<2 x double> %x)
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%cmpinf = fcmp oeq <2 x double> %0, <double 0x7FF0000000000000, double 0x7FF0000000000000>
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ret <2 x i1> %cmpinf
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}
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define zeroext i1 @iszerof(float %x) {
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; P8-LABEL: iszerof:
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; P8: # %bb.0: # %entry
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; P8-NEXT: xxlxor 0, 0, 0
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; P8-NEXT: li 3, 0
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; P8-NEXT: li 4, 1
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; P8-NEXT: fcmpu 0, 1, 0
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; P8-NEXT: iseleq 3, 4, 3
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; P8-NEXT: blr
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;
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; P9-LABEL: iszerof:
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; P9: # %bb.0: # %entry
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; P9-NEXT: xxlxor 0, 0, 0
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; P9-NEXT: li 3, 0
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; P9-NEXT: li 4, 1
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; P9-NEXT: fcmpu 0, 1, 0
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; P9-NEXT: iseleq 3, 4, 3
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; P9-NEXT: blr
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entry:
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%cmp = fcmp oeq float %x, 0.000000e+00
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ret i1 %cmp
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}
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define zeroext i1 @iszero(double %x) {
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; P8-LABEL: iszero:
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; P8: # %bb.0: # %entry
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; P8-NEXT: xxlxor 0, 0, 0
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; P8-NEXT: li 3, 0
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; P8-NEXT: li 4, 1
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; P8-NEXT: fcmpu 0, 1, 0
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; P8-NEXT: iseleq 3, 4, 3
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; P8-NEXT: blr
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;
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; P9-LABEL: iszero:
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; P9: # %bb.0: # %entry
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; P9-NEXT: xxlxor 0, 0, 0
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; P9-NEXT: li 3, 0
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; P9-NEXT: li 4, 1
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; P9-NEXT: fcmpu 0, 1, 0
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; P9-NEXT: iseleq 3, 4, 3
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; P9-NEXT: blr
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entry:
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%cmp = fcmp oeq double %x, 0.000000e+00
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ret i1 %cmp
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}
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define zeroext i1 @iszeroq(fp128 %x) {
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; P8-LABEL: iszeroq:
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; P8: # %bb.0: # %entry
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; P8-NEXT: mflr 0
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; P8-NEXT: stdu 1, -32(1)
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; P8-NEXT: std 0, 48(1)
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; P8-NEXT: .cfi_def_cfa_offset 32
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; P8-NEXT: .cfi_offset lr, 16
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; P8-NEXT: addis 3, 2, .LCPI7_0@toc@ha
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; P8-NEXT: addi 3, 3, .LCPI7_0@toc@l
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; P8-NEXT: lxvd2x 0, 0, 3
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; P8-NEXT: xxswapd 35, 0
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; P8-NEXT: bl __eqkf2
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; P8-NEXT: nop
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; P8-NEXT: cntlzw 3, 3
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; P8-NEXT: srwi 3, 3, 5
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; P8-NEXT: addi 1, 1, 32
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; P8-NEXT: ld 0, 16(1)
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; P8-NEXT: mtlr 0
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; P8-NEXT: blr
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;
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; P9-LABEL: iszeroq:
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; P9: # %bb.0: # %entry
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; P9-NEXT: addis 3, 2, .LCPI7_0@toc@ha
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; P9-NEXT: li 4, 1
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; P9-NEXT: addi 3, 3, .LCPI7_0@toc@l
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; P9-NEXT: lxv 35, 0(3)
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; P9-NEXT: li 3, 0
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; P9-NEXT: xscmpuqp 0, 2, 3
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; P9-NEXT: iseleq 3, 4, 3
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; P9-NEXT: blr
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entry:
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%cmp = fcmp oeq fp128 %x, 0xL00000000000000000000000000000000
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ret i1 %cmp
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}
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define <4 x i1> @iszerov4f32(<4 x float> %x) {
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; P8-LABEL: iszerov4f32:
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; P8: # %bb.0: # %entry
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; P8-NEXT: xxlxor 0, 0, 0
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; P8-NEXT: xvcmpeqsp 34, 34, 0
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; P8-NEXT: blr
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;
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; P9-LABEL: iszerov4f32:
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; P9: # %bb.0: # %entry
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; P9-NEXT: xxlxor 0, 0, 0
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; P9-NEXT: xvcmpeqsp 34, 34, 0
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; P9-NEXT: blr
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entry:
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%cmp = fcmp oeq <4 x float> %x, <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>
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ret <4 x i1> %cmp
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}
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define <2 x i1> @iszerov2f64(<2 x double> %x) {
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; P8-LABEL: iszerov2f64:
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; P8: # %bb.0: # %entry
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; P8-NEXT: xxlxor 0, 0, 0
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; P8-NEXT: xvcmpeqdp 34, 34, 0
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; P8-NEXT: blr
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;
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; P9-LABEL: iszerov2f64:
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; P9: # %bb.0: # %entry
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; P9-NEXT: xxlxor 0, 0, 0
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; P9-NEXT: xvcmpeqdp 34, 34, 0
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; P9-NEXT: blr
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entry:
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%cmp = fcmp oeq <2 x double> %x, <double 0.000000e+00, double 0.000000e+00>
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ret <2 x i1> %cmp
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}
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declare float @llvm.fabs.f32(float)
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declare double @llvm.fabs.f64(double)
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declare fp128 @llvm.fabs.f128(fp128)
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declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
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declare <2 x double> @llvm.fabs.v2f64(<2 x double>)
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