forked from OSchip/llvm-project
[AArch64, X86] Guard against both instrs being wild cards
If both instrs are wild cards, the result can be a crash. llvm-svn: 295776
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@ -34,12 +34,13 @@ static bool shouldScheduleAdjacent(const AArch64InstrInfo &TII,
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const AArch64Subtarget &ST,
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const MachineInstr *First,
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const MachineInstr *Second) {
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assert((First || Second) && "At least one instr must be specified");
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unsigned FirstOpcode =
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First ? First->getOpcode()
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: static_cast<unsigned>(AArch64::INSTRUCTION_LIST_END);
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First ? First->getOpcode()
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: static_cast<unsigned>(AArch64::INSTRUCTION_LIST_END);
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unsigned SecondOpcode =
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Second ? Second->getOpcode()
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: static_cast<unsigned>(AArch64::INSTRUCTION_LIST_END);
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Second ? Second->getOpcode()
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: static_cast<unsigned>(AArch64::INSTRUCTION_LIST_END);
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if (ST.hasArithmeticBccFusion())
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// Fuse CMN, CMP, TST followed by Bcc.
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@ -44,12 +44,13 @@ static bool shouldScheduleAdjacent(const X86Subtarget &ST,
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FuseInc
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} FuseKind;
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assert((First || Second) && "At least one instr must be specified");
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unsigned FirstOpcode = First
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? First->getOpcode()
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: static_cast<unsigned>(X86::INSTRUCTION_LIST_END);
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unsigned SecondOpcode =
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Second ? Second->getOpcode()
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: static_cast<unsigned>(X86::INSTRUCTION_LIST_END);
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? First->getOpcode()
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: static_cast<unsigned>(X86::INSTRUCTION_LIST_END);
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unsigned SecondOpcode = Second
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? Second->getOpcode()
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: static_cast<unsigned>(X86::INSTRUCTION_LIST_END);
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switch (SecondOpcode) {
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default:
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@ -215,7 +216,7 @@ void X86MacroFusion::apply(ScheduleDAGInstrs *DAGInstrs) {
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// For now, assume targets can only fuse with the branch.
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SUnit &ExitSU = DAG->ExitSU;
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MachineInstr *Branch = ExitSU.getInstr();
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if (!shouldScheduleAdjacent(ST, nullptr, Branch))
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if (!Branch || !shouldScheduleAdjacent(ST, nullptr, Branch))
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return;
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for (SDep &PredDep : ExitSU.Preds) {
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