forked from OSchip/llvm-project
Patterns to match AVX 256-bit arithmetic intrinsics
llvm-svn: 110425
This commit is contained in:
Bruno Cardoso Lopes
parent
e8bb340203
commit
b9ad94fbf7
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@ -142,7 +142,7 @@ multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
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!if(Is2Addr,
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!strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
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[(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_",
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!strconcat(SSEVer, !strconcat("_",
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!strconcat(OpcodeStr, FPSizeStr))))
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RC:$src1, RC:$src2))], d>;
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@ -150,7 +150,7 @@ multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
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!if(Is2Addr,
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!strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
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[(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_",
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!strconcat(SSEVer, !strconcat("_",
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!strconcat(OpcodeStr, FPSizeStr))))
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RC:$src1, (mem_frag addr:$src2)))], d>;
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@ -1643,6 +1643,9 @@ let isCommutable = 0 in
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///
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/// These three forms can each be reg+reg or reg+mem.
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///
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/// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
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/// classes below
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multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
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bit Is2Addr = 1> {
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defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
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@ -1682,14 +1685,24 @@ multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
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multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
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bit Is2Addr = 1> {
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defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
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!strconcat(OpcodeStr, "ps"), "", "_ps", f128mem, memopv4f32,
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!strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
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SSEPackedSingle, Is2Addr>, TB;
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defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
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!strconcat(OpcodeStr, "pd"), "2", "_pd", f128mem, memopv2f64,
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!strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
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SSEPackedDouble, Is2Addr>, TB, OpSize;
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}
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multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
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defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
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!strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
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SSEPackedSingle, 0>, TB;
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defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
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!strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
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SSEPackedDouble, 0>, TB, OpSize;
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}
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// Binary Arithmetic instructions
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let isAsmParserOnly = 1 in {
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defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
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@ -1714,11 +1727,13 @@ let isAsmParserOnly = 1 in {
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basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
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basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
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basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
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basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>, VEX_4V;
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basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
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basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
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defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
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basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
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basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
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basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
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basic_sse12_fp_binop_p_y_int<0x5D, "min">,
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basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
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}
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}
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@ -1830,6 +1845,16 @@ multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
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[(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
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}
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/// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
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multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
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Intrinsic V4F32Int> {
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def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
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!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (V4F32Int VR256:$src))]>;
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def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
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!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
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}
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/// sse2_fp_unop_s - SSE2 unops in scalar form.
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multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
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@ -1900,6 +1925,17 @@ multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
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[(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
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}
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/// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
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multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
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Intrinsic V2F64Int> {
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def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (V2F64Int VR256:$src))]>;
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def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
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!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
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}
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let isAsmParserOnly = 1, Predicates = [HasAVX] in {
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// Square root.
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defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
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@ -1910,8 +1946,10 @@ let isAsmParserOnly = 1, Predicates = [HasAVX] in {
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sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
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sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
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sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
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sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
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sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
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sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
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sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
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sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
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VEX;
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// Reciprocal approximations. Note that these typically require refinement
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@ -1920,12 +1958,14 @@ let isAsmParserOnly = 1, Predicates = [HasAVX] in {
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int_x86_sse_rsqrt_ss>, VEX_4V;
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defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
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sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
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sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
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sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
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defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
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VEX_4V;
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defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
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sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
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sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
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sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
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}
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@ -3327,12 +3367,10 @@ let isAsmParserOnly = 1, Predicates = [HasAVX],
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f128mem, 0>, XD, VEX_4V;
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defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
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f128mem, 0>, OpSize, VEX_4V;
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let Pattern = []<dag> in {
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defm VADDSUBPSY : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR256,
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defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
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f256mem, 0>, XD, VEX_4V;
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defm VADDSUBPDY : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR256,
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defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
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f256mem, 0>, OpSize, VEX_4V;
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}
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}
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let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
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ExeDomain = SSEPackedDouble in {
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@ -4350,44 +4388,44 @@ def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
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// SSE4.1 - Round Instructions
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//===----------------------------------------------------------------------===//
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multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
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string OpcodeStr,
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Intrinsic V4F32Int,
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Intrinsic V2F64Int> {
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multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
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X86MemOperand x86memop, RegisterClass RC,
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PatFrag mem_frag32, PatFrag mem_frag64,
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Intrinsic V4F32Int, Intrinsic V2F64Int> {
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// Intrinsic operation, reg.
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// Vector intrinsic operation, reg
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def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
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(outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr,
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"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
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[(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
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OpSize;
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// Vector intrinsic operation, mem
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def PSm_Int : Ii8<opcps, MRMSrcMem,
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(outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
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(outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr,
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"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
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[(set RC:$dst,
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(V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
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TA, OpSize,
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Requires<[HasSSE41]>;
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// Vector intrinsic operation, reg
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def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
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(outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr,
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"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
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[(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
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OpSize;
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// Vector intrinsic operation, mem
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def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
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(outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
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(outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
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!strconcat(OpcodeStr,
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"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
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[(set RC:$dst,
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(V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
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OpSize;
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}
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@ -4508,12 +4546,18 @@ multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
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// FP round - roundss, roundps, roundsd, roundpd
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let isAsmParserOnly = 1, Predicates = [HasAVX] in {
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// Intrinsic form
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defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround",
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int_x86_sse41_round_ps, int_x86_sse41_round_pd>,
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VEX;
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defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
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memopv4f32, memopv2f64,
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int_x86_sse41_round_ps,
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int_x86_sse41_round_pd>, VEX;
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defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
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memopv8f32, memopv4f64,
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int_x86_avx_round_ps_256,
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int_x86_avx_round_pd_256>, VEX;
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defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
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int_x86_sse41_round_ss, int_x86_sse41_round_sd,
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0>, VEX_4V;
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int_x86_sse41_round_ss,
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int_x86_sse41_round_sd, 0>, VEX_4V;
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// Instructions for the assembler
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defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
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VEX;
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@ -4522,7 +4566,8 @@ let isAsmParserOnly = 1, Predicates = [HasAVX] in {
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defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
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}
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defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
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defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
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memopv4f32, memopv2f64,
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int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
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let Constraints = "$src1 = $dst" in
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defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
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