forked from OSchip/llvm-project
GlobalISel: Preserve source value information for outgoing byval args
Pass through the original argument IR value in order to preserve the aliasing information in the memcpy memory operands.
This commit is contained in:
Matt Arsenault
parent
61f834cc09
commit
b9a0384983
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@ -23,6 +23,7 @@
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MachineValueType.h"
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#include <cstdint>
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@ -38,7 +39,6 @@ class MachineIRBuilder;
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struct MachinePointerInfo;
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class MachineRegisterInfo;
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class TargetLowering;
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class Value;
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class CallLowering {
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const TargetLowering *TLI;
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@ -65,10 +65,17 @@ public:
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// if the argument was an incoming arg.
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SmallVector<Register, 2> OrigRegs;
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/// Optionally track the original IR value for the argument. This may not be
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/// meaningful in all contexts. This should only be used on for forwarding
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/// through to use for aliasing information in MachinePointerInfo for memory
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/// arguments.
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const Value *OrigValue = nullptr;
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ArgInfo(ArrayRef<Register> Regs, Type *Ty,
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ArrayRef<ISD::ArgFlagsTy> Flags = ArrayRef<ISD::ArgFlagsTy>(),
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bool IsFixed = true)
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: BaseArgInfo(Ty, Flags, IsFixed), Regs(Regs.begin(), Regs.end()) {
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bool IsFixed = true, const Value *OrigValue = nullptr)
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: BaseArgInfo(Ty, Flags, IsFixed), Regs(Regs.begin(), Regs.end()),
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OrigValue(OrigValue) {
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if (!Regs.empty() && Flags.empty())
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this->Flags.push_back(ISD::ArgFlagsTy());
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// FIXME: We should have just one way of saying "no register".
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@ -77,6 +84,11 @@ public:
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"only void types should have no register");
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}
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ArgInfo(ArrayRef<Register> Regs, const Value &OrigValue,
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ArrayRef<ISD::ArgFlagsTy> Flags = ArrayRef<ISD::ArgFlagsTy>(),
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bool IsFixed = true)
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: ArgInfo(Regs, OrigValue.getType(), Flags, IsFixed, &OrigValue) {}
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ArgInfo() : BaseArgInfo() {}
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};
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@ -112,7 +112,7 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &CB,
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unsigned i = 0;
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unsigned NumFixedArgs = CB.getFunctionType()->getNumParams();
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for (auto &Arg : CB.args()) {
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ArgInfo OrigArg{ArgRegs[i], Arg->getType(), getAttributesForArgIdx(CB, i),
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ArgInfo OrigArg{ArgRegs[i], *Arg.get(), getAttributesForArgIdx(CB, i),
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i < NumFixedArgs};
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setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, CB);
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@ -204,7 +204,8 @@ void CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
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// No splitting to do, but we want to replace the original type (e.g. [1 x
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// double] -> double).
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SplitArgs.emplace_back(OrigArg.Regs[0], SplitVTs[0].getTypeForEVT(Ctx),
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OrigArg.Flags[0], OrigArg.IsFixed);
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OrigArg.Flags[0], OrigArg.IsFixed,
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OrigArg.OrigValue);
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return;
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}
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@ -667,18 +668,19 @@ bool CallLowering::handleAssignments(CCState &CCInfo,
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Register StackAddr =
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Handler.getStackAddress(MemSize, Offset, DstMPO, Flags);
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const LLT PtrTy = MRI.getType(StackAddr);
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// FIXME: We do not have access to the original IR value here to
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// preserve the aliasing information.
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MachinePointerInfo SrcMPO(PtrTy.getAddressSpace());
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MachinePointerInfo SrcMPO(Args[i].OrigValue);
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if (!Args[i].OrigValue) {
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// We still need to accurately track the stack address space if we
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// don't know the underlying value.
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const LLT PtrTy = MRI.getType(StackAddr);
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SrcMPO = MachinePointerInfo(PtrTy.getAddressSpace());
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}
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Align DstAlign = std::max(Flags.getNonZeroByValAlign(),
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inferAlignFromPtrInfo(MF, DstMPO));
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// TODO: Theoretically the source value could have a higher alignment,
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// but we don't have that here
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Align SrcAlign = Flags.getNonZeroByValAlign();
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Align SrcAlign = std::max(Flags.getNonZeroByValAlign(),
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inferAlignFromPtrInfo(MF, SrcMPO));
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Handler.copyArgumentMemory(Args[i], StackAddr, Args[i].Regs[0],
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DstMPO, DstAlign, SrcMPO, SrcAlign,
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@ -552,6 +552,11 @@ Align llvm::inferAlignFromPtrInfo(MachineFunction &MF,
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MPO.Offset);
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}
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if (const Value *V = MPO.V.dyn_cast<const Value *>()) {
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const Module *M = MF.getFunction().getParent();
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return V->getPointerAlignment(M->getDataLayout());
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}
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return Align(1);
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}
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@ -462,7 +462,7 @@ bool AArch64CallLowering::lowerFormalArguments(
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if (DL.getTypeStoreSize(Arg.getType()).isZero())
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continue;
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ArgInfo OrigArg{VRegs[i], Arg.getType()};
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ArgInfo OrigArg{VRegs[i], Arg};
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setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F);
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splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
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@ -656,7 +656,7 @@ bool AMDGPUCallLowering::lowerFormalArguments(
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}
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}
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ArgInfo OrigArg(VRegs[Idx], Arg.getType());
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ArgInfo OrigArg(VRegs[Idx], Arg);
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const unsigned OrigArgIdx = Idx + AttributeList::FirstArgIndex;
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setArgFlags(OrigArg, OrigArgIdx, DL, F);
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@ -3916,7 +3916,7 @@ define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0
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; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY20]], [[C6]](s32)
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; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
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; CHECK: G_MEMCPY [[PTR_ADD2]](p5), [[FRAME_INDEX]](p5), [[C7]](s32), 0 :: (dereferenceable store 8 into stack, align 4, addrspace 5), (dereferenceable load 8, align 4, addrspace 5)
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; CHECK: G_MEMCPY [[PTR_ADD2]](p5), [[FRAME_INDEX]](p5), [[C7]](s32), 0 :: (dereferenceable store 8 into stack, align 4, addrspace 5), (dereferenceable load 8 from %ir.val, align 4, addrspace 5)
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; CHECK: [[COPY21:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
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; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY21]](<4 x s32>)
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; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
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@ -3971,11 +3971,11 @@ define void @call_byval_3ai32_byval_i8_align32([3 x i32] addrspace(5)* %incoming
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY19]], [[C1]](s32)
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; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
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; CHECK: G_MEMCPY [[PTR_ADD]](p5), [[COPY8]](p5), [[C2]](s32), 0 :: (dereferenceable store 12 into stack, align 4, addrspace 5), (dereferenceable load 12, align 4, addrspace 5)
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; CHECK: G_MEMCPY [[PTR_ADD]](p5), [[COPY8]](p5), [[C2]](s32), 0 :: (dereferenceable store 12 into stack, align 4, addrspace 5), (dereferenceable load 12 from %ir.incoming0, align 4, addrspace 5)
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; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
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; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY19]], [[C3]](s32)
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; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK: G_MEMCPY [[PTR_ADD1]](p5), [[COPY9]](p5), [[C4]](s32), 0 :: (dereferenceable store 1 into stack + 32, align 32, addrspace 5), (dereferenceable load 1, align 32, addrspace 5)
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; CHECK: G_MEMCPY [[PTR_ADD1]](p5), [[COPY9]](p5), [[C4]](s32), 0 :: (dereferenceable store 1 into stack + 32, align 32, addrspace 5), (dereferenceable load 1 from %ir.incoming1, align 32, addrspace 5)
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; CHECK: $vgpr0 = COPY [[C]](s32)
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; CHECK: [[COPY20:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY20]](<4 x s32>)
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@ -3995,6 +3995,57 @@ define void @call_byval_3ai32_byval_i8_align32([3 x i32] addrspace(5)* %incoming
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ret void
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}
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declare void @void_func_byval_a4i64_align4([4 x i64] addrspace(5)* byval([4 x i64]) align 4 %arg0) #0
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; Make sure we are aware of the higher alignment of the incoming value
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; than implied by the outgoing byval alignment in the memory operand.
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define void @call_byval_a4i64_align4_higher_source_align([4 x i64] addrspace(5)* align 256 %incoming_high_align) #0 {
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; CHECK-LABEL: name: call_byval_a4i64_align4_higher_source_align
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $sgpr12, $sgpr13, $sgpr14, $vgpr0, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr31
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; CHECK: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr14
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; CHECK: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr13
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; CHECK: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr12
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; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
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; CHECK: [[COPY5:%[0-9]+]]:sgpr_64 = COPY $sgpr8_sgpr9
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; CHECK: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
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; CHECK: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
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; CHECK: [[COPY8:%[0-9]+]]:_(p5) = COPY $vgpr0
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; CHECK: [[COPY9:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $scc
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; CHECK: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @void_func_byval_a4i64_align4
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; CHECK: [[COPY10:%[0-9]+]]:_(p4) = COPY [[COPY7]]
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; CHECK: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY6]]
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; CHECK: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY5]]
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; CHECK: [[COPY13:%[0-9]+]]:_(s64) = COPY [[COPY4]]
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; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY3]]
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; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY2]]
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; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY1]]
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; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; CHECK: [[COPY18:%[0-9]+]]:_(p5) = COPY $sgpr32
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY18]], [[C]](s32)
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
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; CHECK: G_MEMCPY [[PTR_ADD]](p5), [[COPY8]](p5), [[C1]](s32), 0 :: (dereferenceable store 32 into stack, align 4, addrspace 5), (dereferenceable load 32 from %ir.incoming_high_align, align 256, addrspace 5)
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; CHECK: [[COPY19:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY19]](<4 x s32>)
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; CHECK: $sgpr4_sgpr5 = COPY [[COPY10]](p4)
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; CHECK: $sgpr6_sgpr7 = COPY [[COPY11]](p4)
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; CHECK: $sgpr8_sgpr9 = COPY [[COPY12]](p4)
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; CHECK: $sgpr10_sgpr11 = COPY [[COPY13]](s64)
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; CHECK: $sgpr12 = COPY [[COPY14]](s32)
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; CHECK: $sgpr13 = COPY [[COPY15]](s32)
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; CHECK: $sgpr14 = COPY [[COPY16]](s32)
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; CHECK: $vgpr31 = COPY [[COPY17]](s32)
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; CHECK: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @void_func_byval_a4i64_align4, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31
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; CHECK: ADJCALLSTACKDOWN 0, 32, implicit-def $scc
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; CHECK: [[COPY20:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY9]]
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; CHECK: S_SETPC_B64_return [[COPY20]]
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call void @void_func_byval_a4i64_align4([4 x i64] addrspace(5)* byval([4 x i64]) align 4 %incoming_high_align)
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ret void
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}
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define amdgpu_kernel void @test_call_external_void_func_v2i8() #0 {
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; CHECK-LABEL: name: test_call_external_void_func_v2i8
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; CHECK: bb.1 (%ir-block.0):
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