forked from OSchip/llvm-project
Add initial support for back-scheduling address computations,
especially in the case of addresses computed from loop induction variables. llvm-svn: 61075
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405f2197a4
commit
b9a012156b
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@ -242,6 +242,7 @@ namespace llvm {
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bool isPending : 1; // True once pending.
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bool isAvailable : 1; // True once available.
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bool isScheduled : 1; // True once scheduled.
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bool isScheduleHigh : 1; // True if preferable to schedule high.
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private:
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bool isDepthCurrent : 1; // True if Depth is current.
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bool isHeightCurrent : 1; // True if Height is current.
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@ -258,7 +259,7 @@ namespace llvm {
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Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
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isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
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isPending(false), isAvailable(false), isScheduled(false),
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isDepthCurrent(false), isHeightCurrent(false),
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isScheduleHigh(false), isDepthCurrent(false), isHeightCurrent(false),
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Depth(0), Height(0),
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CopyDstRC(NULL), CopySrcRC(NULL) {}
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@ -269,7 +270,7 @@ namespace llvm {
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Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
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isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false),
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isPending(false), isAvailable(false), isScheduled(false),
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isDepthCurrent(false), isHeightCurrent(false),
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isScheduleHigh(false), isDepthCurrent(false), isHeightCurrent(false),
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Depth(0), Height(0),
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CopyDstRC(NULL), CopySrcRC(NULL) {}
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@ -29,6 +29,12 @@ protected: // Can only create subclasses...
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TargetSubtarget();
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public:
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virtual ~TargetSubtarget();
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/// getSpecialAddressLatency - For targets where it is beneficial to
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/// backschedule instructions that compute addresses, return a value
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/// indicating the number of scheduling cycles of backscheduling that
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/// should be attempted.
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virtual unsigned getSpecialAddressLatency() const { return 0; }
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};
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} // End llvm namespace
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@ -19,6 +19,14 @@
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using namespace llvm;
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bool latency_sort::operator()(const SUnit *LHS, const SUnit *RHS) const {
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// The isScheduleHigh flag allows nodes with wraparound dependencies that
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// cannot easily be modeled as edges with latencies to be scheduled as
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// soon as possible in a top-down schedule.
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if (LHS->isScheduleHigh && !RHS->isScheduleHigh)
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return false;
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if (!LHS->isScheduleHigh && RHS->isScheduleHigh)
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return true;
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unsigned LHSNum = LHS->NodeNum;
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unsigned RHSNum = RHS->NodeNum;
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@ -15,6 +15,7 @@
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#define DEBUG_TYPE "sched-instrs"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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@ -29,6 +30,59 @@
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#include <map>
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using namespace llvm;
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namespace {
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class VISIBILITY_HIDDEN LoopDependencies {
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const MachineLoopInfo &MLI;
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const MachineDominatorTree &MDT;
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public:
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typedef std::map<unsigned, std::pair<const MachineOperand *, unsigned> >
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LoopDeps;
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LoopDeps Deps;
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LoopDependencies(const MachineLoopInfo &mli,
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const MachineDominatorTree &mdt) :
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MLI(mli), MDT(mdt) {}
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void VisitLoop(const MachineLoop *Loop) {
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Deps.clear();
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MachineBasicBlock *Header = Loop->getHeader();
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SmallSet<unsigned, 8> LoopLiveIns;
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for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(),
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LE = Header->livein_end(); LI != LE; ++LI)
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LoopLiveIns.insert(*LI);
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VisitRegion(MDT.getNode(Header), Loop, LoopLiveIns);
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}
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private:
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void VisitRegion(const MachineDomTreeNode *Node,
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const MachineLoop *Loop,
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const SmallSet<unsigned, 8> &LoopLiveIns) {
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MachineBasicBlock *MBB = Node->getBlock();
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if (!Loop->contains(MBB)) return;
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unsigned Count = 0;
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for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I, ++Count) {
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const MachineInstr *MI = I;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isUse())
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continue;
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unsigned MOReg = MO.getReg();
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if (LoopLiveIns.count(MOReg))
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Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count)));
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}
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}
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const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
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for (unsigned I = 0, E = Children.size(); I != E; ++I)
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VisitRegion(Children[I], Loop, LoopLiveIns);
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}
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};
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}
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ScheduleDAGInstrs::ScheduleDAGInstrs(MachineBasicBlock *bb,
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const TargetMachine &tm,
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const MachineLoopInfo &mli,
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@ -65,9 +119,27 @@ void ScheduleDAGInstrs::BuildSchedUnits() {
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// all the work of the block is done before the terminator.
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SUnit *Terminator = 0;
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LoopDependencies LoopRegs(MLI, MDT);
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// Track which regs are live into a loop, to help guide back-edge-aware
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// scheduling.
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SmallSet<unsigned, 8> LoopLiveInRegs;
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if (MachineLoop *ML = MLI.getLoopFor(BB))
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if (BB == ML->getLoopLatch()) {
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MachineBasicBlock *Header = ML->getHeader();
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for (MachineBasicBlock::livein_iterator I = Header->livein_begin(),
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E = Header->livein_end(); I != E; ++I)
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LoopLiveInRegs.insert(*I);
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LoopRegs.VisitLoop(ML);
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}
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// Check to see if the scheduler cares about latencies.
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bool UnitLatencies = ForceUnitLatencies();
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// Ask the target if address-backscheduling is desirable, and if so how much.
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unsigned SpecialAddressLatency =
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TM.getSubtarget<TargetSubtarget>().getSpecialAddressLatency();
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for (MachineBasicBlock::iterator MII = BB->end(), MIE = BB->begin();
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MII != MIE; --MII) {
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MachineInstr *MI = prior(MII);
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@ -118,7 +190,21 @@ void ScheduleDAGInstrs::BuildSchedUnits() {
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for (unsigned i = 0, e = UseList.size(); i != e; ++i) {
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SUnit *UseSU = UseList[i];
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if (UseSU != SU) {
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UseSU->addPred(SDep(SU, SDep::Data, DataLatency, Reg));
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unsigned LDataLatency = DataLatency;
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// Optionally add in a special extra latency for nodes that
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// feed addresses.
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// TODO: Do this for register aliases too.
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if (SpecialAddressLatency != 0 && !UnitLatencies) {
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MachineInstr *UseMI = UseSU->getInstr();
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const TargetInstrDesc &UseTID = UseMI->getDesc();
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int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg);
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assert(RegUseIndex >= 0 && "UseMI doesn's use register!");
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if ((UseTID.mayLoad() || UseTID.mayStore()) &&
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(unsigned)RegUseIndex < UseTID.getNumOperands() &&
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UseTID.OpInfo[RegUseIndex].isLookupPtrRegClass())
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LDataLatency += SpecialAddressLatency;
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}
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UseSU->addPred(SDep(SU, SDep::Data, LDataLatency, Reg));
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}
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}
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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@ -130,6 +216,51 @@ void ScheduleDAGInstrs::BuildSchedUnits() {
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}
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}
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// If a def is going to wrap back around to the top of the loop,
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// backschedule it.
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// TODO: Blocks in loops without terminators can benefit too.
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if (!UnitLatencies && Terminator && DefList.empty()) {
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LoopDependencies::LoopDeps::iterator I = LoopRegs.Deps.find(Reg);
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if (I != LoopRegs.Deps.end()) {
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const MachineOperand *UseMO = I->second.first;
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unsigned Count = I->second.second;
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const MachineInstr *UseMI = UseMO->getParent();
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unsigned UseMOIdx = UseMO - &UseMI->getOperand(0);
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const TargetInstrDesc &UseTID = UseMI->getDesc();
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// TODO: If we knew the total depth of the region here, we could
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// handle the case where the whole loop is inside the region but
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// is large enough that the isScheduleHigh trick isn't needed.
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if (UseMOIdx < UseTID.getNumOperands()) {
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// Currently, we only support scheduling regions consisting of
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// single basic blocks. Check to see if the instruction is in
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// the same region by checking to see if it has the same parent.
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if (UseMI->getParent() != MI->getParent()) {
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unsigned Latency = SU->Latency;
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if (UseTID.OpInfo[UseMOIdx].isLookupPtrRegClass())
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Latency += SpecialAddressLatency;
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// This is a wild guess as to the portion of the latency which
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// will be overlapped by work done outside the current
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// scheduling region.
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Latency -= std::min(Latency, Count);
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// Add the artifical edge.
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Terminator->addPred(SDep(SU, SDep::Order, Latency,
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/*Reg=*/0, /*isNormalMemory=*/false,
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/*isMustAlias=*/false,
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/*isArtificial=*/true));
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} else if (SpecialAddressLatency > 0 &&
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UseTID.OpInfo[UseMOIdx].isLookupPtrRegClass()) {
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// The entire loop body is within the current scheduling region
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// and the latency of this operation is assumed to be greater
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// than the latency of the loop.
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// TODO: Recursively mark data-edge predecessors as
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// isScheduleHigh too.
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SU->isScheduleHigh = true;
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}
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}
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LoopRegs.Deps.erase(I);
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}
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}
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UseList.clear();
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if (!MO.isDead())
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DefList.clear();
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@ -93,6 +93,17 @@ const char *X86Subtarget::getBZeroEntry() const {
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return 0;
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}
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/// getSpecialAddressLatency - For targets where it is beneficial to
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/// backschedule instructions that compute addresses, return a value
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/// indicating the number of scheduling cycles of backscheduling that
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/// should be attempted.
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unsigned X86Subtarget::getSpecialAddressLatency() const {
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// For x86 out-of-order targets, back-schedule address computations so
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// that loads and stores aren't blocked.
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// This value was chosen arbitrarily.
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return 200;
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}
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/// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
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/// specified arguments. If we can't run cpuid on the host, return true.
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bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
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@ -191,6 +191,12 @@ public:
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/// memset with zero passed as the second argument. Otherwise it
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/// returns null.
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const char *getBZeroEntry() const;
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/// getSpecialAddressLatency - For targets where it is beneficial to
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/// backschedule instructions that compute addresses, return a value
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/// indicating the number of scheduling cycles of backscheduling that
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/// should be attempted.
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unsigned getSpecialAddressLatency() const;
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};
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namespace X86 {
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