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[Hexagon] Add pattern to generate 64-bit neg instruction 

llvm-svn: 334043
This commit is contained in:
Krzysztof Parzyszek 2018-06-05 19:52:39 +00:00
parent d8b093efef
commit b984ffcc71
3 changed files with 22 additions and 18 deletions
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9
llvm/lib/Target/Hexagon/HexagonPatterns.td
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@ -1157,10 +1157,11 @@ def: Pat<(shl V4I16:$b, (v4i16 (HexagonVSPLAT u4_0ImmPred:$c))),
// --(9) Arithmetic/bitwise ----------------------------------------------
//
def: Pat<(abs I32:$Rs), (A2_abs I32:$Rs)>;
def: Pat<(abs I64:$Rs), (A2_absp I64:$Rs)>;
def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>;
def: Pat<(not I64:$Rs), (A2_notp I64:$Rs)>;
def: Pat<(abs I32:$Rs), (A2_abs I32:$Rs)>;
def: Pat<(abs I64:$Rs), (A2_absp I64:$Rs)>;
def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>;
def: Pat<(not I64:$Rs), (A2_notp I64:$Rs)>;
def: Pat<(ineg I64:$Rs), (A2_negp I64:$Rs)>;
let Predicates = [HasV5T] in {
def: Pat<(fabs F32:$Rs), (S2_clrbit_i F32:$Rs, 31)>;

14
llvm/test/CodeGen/Hexagon/neg-op.ll
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@ -1,14 +0,0 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: r{{[0-9]+}} = sub(#0,r{{[0-9]+}})
; Function Attrs: nounwind
define i32 @f0(i32 %a0) #0 {
b0:
%v0 = alloca i32, align 4
store i32 %a0, i32* %v0, align 4
%v1 = load i32, i32* %v0, align 4
%v2 = sub nsw i32 0, %v1
ret i32 %v2
}
attributes #0 = { nounwind }

17
llvm/test/CodeGen/Hexagon/neg.ll Normal file
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@ -0,0 +1,17 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK-LABEL: f0:
; CHECK: r0 = sub(#0,r0)
define i32 @f0(i32 %a0) #0 {
%v0 = sub i32 0, %a0
ret i32 %v0
}
; CHECK-LABEL: f1:
; CHECK: r1:0 = neg(r1:0)
define i64 @f1(i64 %a0) #0 {
%v0 = sub i64 0, %a0
ret i64 %v0
}
attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" }