forked from OSchip/llvm-project
AMDGPU: Remove llvm.AMDGPU.cube intrinsic
llvm-svn: 295359
This commit is contained in:
Matt Arsenault
parent
eb65cda986
commit
b95ddd7cea
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@ -64,6 +64,10 @@ def int_r600_recipsqrt_clamped : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
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>;
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def int_r600_cube : Intrinsic<
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[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]
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>;
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} // End TargetPrefix = "r600"
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let TargetPrefix = "amdgcn" in {
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@ -20,9 +20,6 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in {
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// Deprecated in favor of llvm.amdgcn.sffbh
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def int_AMDGPU_flbit_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
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// Deprecated in favor of separate int_amdgcn_cube* intrinsics.
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def int_AMDGPU_cube : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
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// Deprecated in favor of expanded bit operations
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def int_AMDGPU_bfe_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_bfe_u32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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@ -1013,7 +1013,7 @@ multiclass CUBE_Common <bits<11> inst> {
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(outs R600_Reg128:$dst),
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(ins R600_Reg128:$src0),
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"CUBE $dst $src0",
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[(set v4f32:$dst, (int_AMDGPU_cube v4f32:$src0))],
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[(set v4f32:$dst, (int_r600_cube v4f32:$src0))],
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VecALU
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> {
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let isPseudo = 1;
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@ -817,27 +817,6 @@ def : Pat <
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def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>;
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def : Pat <
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(int_AMDGPU_cube v4f32:$src),
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(REG_SEQUENCE VReg_128,
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(V_CUBETC_F32 0 /* src0_modifiers */, (f32 (EXTRACT_SUBREG $src, sub0)),
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0 /* src1_modifiers */, (f32 (EXTRACT_SUBREG $src, sub1)),
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0 /* src2_modifiers */, (f32 (EXTRACT_SUBREG $src, sub2)),
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0 /* clamp */, 0 /* omod */), sub0,
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(V_CUBESC_F32 0 /* src0_modifiers */, (f32 (EXTRACT_SUBREG $src, sub0)),
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0 /* src1_modifiers */,(f32 (EXTRACT_SUBREG $src, sub1)),
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0 /* src2_modifiers */,(f32 (EXTRACT_SUBREG $src, sub2)),
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0 /* clamp */, 0 /* omod */), sub1,
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(V_CUBEMA_F32 0 /* src1_modifiers */,(f32 (EXTRACT_SUBREG $src, sub0)),
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0 /* src1_modifiers */,(f32 (EXTRACT_SUBREG $src, sub1)),
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0 /* src1_modifiers */,(f32 (EXTRACT_SUBREG $src, sub2)),
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0 /* clamp */, 0 /* omod */), sub2,
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(V_CUBEID_F32 0 /* src1_modifiers */,(f32 (EXTRACT_SUBREG $src, sub0)),
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0 /* src1_modifiers */,(f32 (EXTRACT_SUBREG $src, sub1)),
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0 /* src1_modifiers */,(f32 (EXTRACT_SUBREG $src, sub2)),
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0 /* clamp */, 0 /* omod */), sub3)
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>;
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def : Pat <
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(i32 (sext i1:$src0)),
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(V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0)
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@ -6,9 +6,6 @@ declare float @llvm.amdgcn.cubesc(float, float, float) #0
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declare float @llvm.amdgcn.cubetc(float, float, float) #0
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declare float @llvm.amdgcn.cubema(float, float, float) #0
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declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #0
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; GCN-LABEL: {{^}}cube:
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; GCN-DAG: v_cubeid_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-DAG: v_cubesc_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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@ -29,18 +26,5 @@ define void @cube(<4 x float> addrspace(1)* %out, float %a, float %b, float %c)
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ret void
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}
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; GCN-LABEL: {{^}}legacy_cube:
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; GCN-DAG: v_cubeid_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}
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; GCN-DAG: v_cubesc_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}
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; GCN-DAG: v_cubetc_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}
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; GCN-DAG: v_cubema_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}
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; GCN: _store_dwordx4
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define void @legacy_cube(<4 x float> addrspace(1)* %out, <4 x float> %abcx) #1 {
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%cube = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %abcx)
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store <4 x float> %cube, <4 x float> addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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@ -22,7 +22,7 @@ main_body:
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%tmp12 = insertelement <4 x float> %tmp11, float %tmp7, i32 1
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%tmp13 = insertelement <4 x float> %tmp12, float %tmp10, i32 2
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%tmp14 = insertelement <4 x float> %tmp13, float 1.000000e+00, i32 3
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%tmp15 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %tmp14)
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%tmp15 = call <4 x float> @llvm.r600.cube(<4 x float> %tmp14)
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%tmp16 = extractelement <4 x float> %tmp15, i32 0
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%tmp17 = extractelement <4 x float> %tmp15, i32 1
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%tmp18 = extractelement <4 x float> %tmp15, i32 2
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@ -44,7 +44,7 @@ main_body:
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}
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; Function Attrs: readnone
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declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #0
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declare <4 x float> @llvm.r600.cube(<4 x float>) #0
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; Function Attrs: nounwind readnone
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declare float @llvm.fabs.f32(float) #0
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@ -10,7 +10,7 @@ main_body:
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%tmp6 = insertelement <4 x float> %tmp5, float %tmp2, i32 1
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%tmp7 = insertelement <4 x float> %tmp6, float %tmp3, i32 2
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%tmp8 = insertelement <4 x float> %tmp7, float %tmp4, i32 3
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%tmp9 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %tmp8)
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%tmp9 = call <4 x float> @llvm.r600.cube(<4 x float> %tmp8)
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%tmp10 = extractelement <4 x float> %tmp9, i32 0
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%tmp11 = extractelement <4 x float> %tmp9, i32 1
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%tmp12 = extractelement <4 x float> %tmp9, i32 2
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@ -45,7 +45,7 @@ main_body:
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}
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; Function Attrs: readnone
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declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #0
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declare <4 x float> @llvm.r600.cube(<4 x float>) #0
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; Function Attrs: readnone
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declare float @fabs(float) #0
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@ -586,7 +586,19 @@ IF67: ; preds = %LOOP65
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%tmp449 = insertelement <4 x float> %tmp448, float %tmp445, i32 1
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%tmp450 = insertelement <4 x float> %tmp449, float %tmp447, i32 2
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%tmp451 = insertelement <4 x float> %tmp450, float %tmp194, i32 3
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%tmp452 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %tmp451)
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%tmp451.x = extractelement <4 x float> %tmp451, i32 0
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%tmp451.y = extractelement <4 x float> %tmp451, i32 1
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%tmp451.z = extractelement <4 x float> %tmp451, i32 2
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%cubetc = call float @llvm.amdgcn.cubetc(float %tmp451.x, float %tmp451.y, float %tmp451.z)
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%cubesc = call float @llvm.amdgcn.cubesc(float %tmp451.x, float %tmp451.y, float %tmp451.z)
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%cubema = call float @llvm.amdgcn.cubema(float %tmp451.x, float %tmp451.y, float %tmp451.z)
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%cubeid = call float @llvm.amdgcn.cubeid(float %tmp451.x, float %tmp451.y, float %tmp451.z)
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%tmp452.0 = insertelement <4 x float> undef, float %cubetc, i32 0
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%tmp452.1 = insertelement <4 x float> %tmp452.0, float %cubesc, i32 1
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%tmp452.2 = insertelement <4 x float> %tmp452.1, float %cubema, i32 2
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%tmp452 = insertelement <4 x float> %tmp452.2, float %cubeid, i32 3
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%tmp453 = extractelement <4 x float> %tmp452, i32 0
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%tmp454 = extractelement <4 x float> %tmp452, i32 1
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%tmp455 = extractelement <4 x float> %tmp452, i32 2
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@ -1840,9 +1852,6 @@ declare float @llvm.amdgcn.rsq.f32(float) #0
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.SI.image.sample.d.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #0
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; Function Attrs: nounwind readnone
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declare float @llvm.fabs.f32(float) #0
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@ -1863,6 +1872,11 @@ declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #0
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; Function Attrs: nounwind readnone
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declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #0
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declare float @llvm.amdgcn.cubeid(float, float, float) #0
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declare float @llvm.amdgcn.cubesc(float, float, float) #0
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declare float @llvm.amdgcn.cubetc(float, float, float) #0
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declare float @llvm.amdgcn.cubema(float, float, float) #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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