forked from OSchip/llvm-project
[x86] add tests for heroic horizontal ops; NFC
This commit is contained in:
Sanjay Patel
parent
9d7838d781
commit
b95a542d6b
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@ -875,3 +875,174 @@ define <4 x float> @broadcast_haddps_v4f32(<4 x float> %a0) {
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}
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declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>)
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define <4 x float> @PR34724_1(<4 x float> %a, <4 x float> %b) {
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; SSSE3_SLOW-LABEL: PR34724_1:
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; SSSE3_SLOW: # %bb.0:
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; SSSE3_SLOW-NEXT: movaps %xmm1, %xmm2
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; SSSE3_SLOW-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm0[3,2]
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; SSSE3_SLOW-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3]
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; SSSE3_SLOW-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
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; SSSE3_SLOW-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; SSSE3_SLOW-NEXT: addps %xmm0, %xmm2
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; SSSE3_SLOW-NEXT: movsldup {{.*#+}} xmm0 = xmm1[0,0,2,2]
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; SSSE3_SLOW-NEXT: addps %xmm1, %xmm0
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; SSSE3_SLOW-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm2[1,0]
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; SSSE3_SLOW-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm0[2,0]
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; SSSE3_SLOW-NEXT: movaps %xmm2, %xmm0
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; SSSE3_SLOW-NEXT: retq
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;
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; SSSE3_FAST-LABEL: PR34724_1:
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; SSSE3_FAST: # %bb.0:
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; SSSE3_FAST-NEXT: movaps %xmm1, %xmm2
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; SSSE3_FAST-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm0[3,2]
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; SSSE3_FAST-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3]
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; SSSE3_FAST-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
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; SSSE3_FAST-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; SSSE3_FAST-NEXT: addps %xmm0, %xmm2
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; SSSE3_FAST-NEXT: haddps %xmm1, %xmm1
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; SSSE3_FAST-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[1,0]
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; SSSE3_FAST-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[2,0]
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; SSSE3_FAST-NEXT: movaps %xmm2, %xmm0
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; SSSE3_FAST-NEXT: retq
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;
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; AVX1_SLOW-LABEL: PR34724_1:
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; AVX1_SLOW: # %bb.0:
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; AVX1_SLOW-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
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; AVX1_SLOW-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm1[0],zero,zero
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; AVX1_SLOW-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[3],xmm1[1],zero,zero
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; AVX1_SLOW-NEXT: vaddps %xmm0, %xmm2, %xmm0
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; AVX1_SLOW-NEXT: vmovsldup {{.*#+}} xmm2 = xmm1[0,0,2,2]
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; AVX1_SLOW-NEXT: vaddps %xmm1, %xmm2, %xmm1
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; AVX1_SLOW-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX1_SLOW-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,3]
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; AVX1_SLOW-NEXT: retq
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;
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; AVX1_FAST-LABEL: PR34724_1:
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; AVX1_FAST: # %bb.0:
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; AVX1_FAST-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
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; AVX1_FAST-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm1[0],zero,zero
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; AVX1_FAST-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[3],xmm1[1],zero,zero
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; AVX1_FAST-NEXT: vaddps %xmm0, %xmm2, %xmm0
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; AVX1_FAST-NEXT: vhaddps %xmm1, %xmm1, %xmm1
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; AVX1_FAST-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX1_FAST-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,3]
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; AVX1_FAST-NEXT: retq
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;
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; AVX2_SLOW-LABEL: PR34724_1:
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; AVX2_SLOW: # %bb.0:
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; AVX2_SLOW-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
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; AVX2_SLOW-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm1[0],zero,zero
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; AVX2_SLOW-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[3],xmm1[1],zero,zero
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; AVX2_SLOW-NEXT: vaddps %xmm0, %xmm2, %xmm0
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; AVX2_SLOW-NEXT: vmovsldup {{.*#+}} xmm2 = xmm1[0,0,2,2]
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; AVX2_SLOW-NEXT: vaddps %xmm1, %xmm2, %xmm1
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; AVX2_SLOW-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX2_SLOW-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,3]
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; AVX2_SLOW-NEXT: retq
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;
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; AVX2_FAST-LABEL: PR34724_1:
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; AVX2_FAST: # %bb.0:
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; AVX2_FAST-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
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; AVX2_FAST-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],xmm1[0],zero,zero
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; AVX2_FAST-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[3],xmm1[1],zero,zero
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; AVX2_FAST-NEXT: vaddps %xmm0, %xmm2, %xmm0
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; AVX2_FAST-NEXT: vhaddps %xmm1, %xmm1, %xmm1
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; AVX2_FAST-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX2_FAST-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,3]
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; AVX2_FAST-NEXT: retq
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%t0 = shufflevector <4 x float> %a, <4 x float> %b, <2 x i32> <i32 2, i32 4>
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%t1 = shufflevector <4 x float> %a, <4 x float> %b, <2 x i32> <i32 3, i32 5>
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%t2 = fadd <2 x float> %t0, %t1
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%vecinit9 = shufflevector <2 x float> %t2, <2 x float> undef, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef>
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%t3 = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 2>
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%t4 = fadd <4 x float> %t3, %b
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%vecinit13 = shufflevector <4 x float> %vecinit9, <4 x float> %t4, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
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ret <4 x float> %vecinit13
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}
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define <4 x float> @PR34724_2(<4 x float> %a, <4 x float> %b) {
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; SSSE3_SLOW-LABEL: PR34724_2:
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; SSSE3_SLOW: # %bb.0:
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; SSSE3_SLOW-NEXT: movaps %xmm1, %xmm2
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; SSSE3_SLOW-NEXT: movsldup {{.*#+}} xmm3 = xmm1[0,0,2,2]
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; SSSE3_SLOW-NEXT: addps %xmm1, %xmm3
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; SSSE3_SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[2,0]
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; SSSE3_SLOW-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
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; SSSE3_SLOW-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm0[3,0]
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; SSSE3_SLOW-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3]
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; SSSE3_SLOW-NEXT: addps %xmm1, %xmm2
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; SSSE3_SLOW-NEXT: shufps {{.*#+}} xmm3 = xmm3[3,0],xmm2[1,0]
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; SSSE3_SLOW-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm3[2,0]
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; SSSE3_SLOW-NEXT: movaps %xmm2, %xmm0
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; SSSE3_SLOW-NEXT: retq
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;
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; SSSE3_FAST-LABEL: PR34724_2:
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; SSSE3_FAST: # %bb.0:
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; SSSE3_FAST-NEXT: movaps %xmm1, %xmm3
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; SSSE3_FAST-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,0],xmm0[2,0]
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; SSSE3_FAST-NEXT: shufps {{.*#+}} xmm3 = xmm3[2,0],xmm0[2,3]
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; SSSE3_FAST-NEXT: movaps %xmm1, %xmm2
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; SSSE3_FAST-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,0],xmm0[3,0]
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; SSSE3_FAST-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm0[2,3]
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; SSSE3_FAST-NEXT: addps %xmm3, %xmm2
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; SSSE3_FAST-NEXT: haddps %xmm1, %xmm1
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; SSSE3_FAST-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm2[1,0]
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; SSSE3_FAST-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[2,0]
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; SSSE3_FAST-NEXT: movaps %xmm2, %xmm0
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; SSSE3_FAST-NEXT: retq
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;
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; AVX1_SLOW-LABEL: PR34724_2:
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; AVX1_SLOW: # %bb.0:
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; AVX1_SLOW-NEXT: vblendps {{.*#+}} xmm2 = xmm1[0,1],xmm0[2,3]
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; AVX1_SLOW-NEXT: vpermilps {{.*#+}} xmm2 = xmm2[2,0,2,3]
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; AVX1_SLOW-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[3],xmm1[1],zero,zero
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; AVX1_SLOW-NEXT: vaddps %xmm0, %xmm2, %xmm0
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; AVX1_SLOW-NEXT: vmovsldup {{.*#+}} xmm2 = xmm1[0,0,2,2]
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; AVX1_SLOW-NEXT: vaddps %xmm1, %xmm2, %xmm1
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; AVX1_SLOW-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX1_SLOW-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,3]
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; AVX1_SLOW-NEXT: retq
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;
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; AVX1_FAST-LABEL: PR34724_2:
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; AVX1_FAST: # %bb.0:
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; AVX1_FAST-NEXT: vblendps {{.*#+}} xmm2 = xmm1[0,1],xmm0[2,3]
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; AVX1_FAST-NEXT: vpermilps {{.*#+}} xmm2 = xmm2[2,0,2,3]
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; AVX1_FAST-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[3],xmm1[1],zero,zero
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; AVX1_FAST-NEXT: vaddps %xmm0, %xmm2, %xmm0
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; AVX1_FAST-NEXT: vhaddps %xmm1, %xmm1, %xmm1
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; AVX1_FAST-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX1_FAST-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,3]
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; AVX1_FAST-NEXT: retq
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;
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; AVX2_SLOW-LABEL: PR34724_2:
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; AVX2_SLOW: # %bb.0:
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; AVX2_SLOW-NEXT: vblendps {{.*#+}} xmm2 = xmm1[0,1],xmm0[2,3]
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; AVX2_SLOW-NEXT: vpermilps {{.*#+}} xmm2 = xmm2[2,0,2,3]
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; AVX2_SLOW-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[3],xmm1[1],zero,zero
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; AVX2_SLOW-NEXT: vaddps %xmm0, %xmm2, %xmm0
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; AVX2_SLOW-NEXT: vmovsldup {{.*#+}} xmm2 = xmm1[0,0,2,2]
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; AVX2_SLOW-NEXT: vaddps %xmm1, %xmm2, %xmm1
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; AVX2_SLOW-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX2_SLOW-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,3]
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; AVX2_SLOW-NEXT: retq
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;
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; AVX2_FAST-LABEL: PR34724_2:
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; AVX2_FAST: # %bb.0:
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; AVX2_FAST-NEXT: vblendps {{.*#+}} xmm2 = xmm1[0,1],xmm0[2,3]
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; AVX2_FAST-NEXT: vpermilps {{.*#+}} xmm2 = xmm2[2,0,2,3]
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; AVX2_FAST-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[3],xmm1[1],zero,zero
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; AVX2_FAST-NEXT: vaddps %xmm0, %xmm2, %xmm0
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; AVX2_FAST-NEXT: vhaddps %xmm1, %xmm1, %xmm1
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; AVX2_FAST-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
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; AVX2_FAST-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,3]
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; AVX2_FAST-NEXT: retq
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%t0 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 4, i32 undef, i32 undef>
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%t1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 3, i32 5, i32 undef, i32 undef>
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%t2 = fadd <4 x float> %t0, %t1
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%vecinit9 = shufflevector <4 x float> %t2, <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef>
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%t3 = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 2>
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%t4 = fadd <4 x float> %t3, %b
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%vecinit13 = shufflevector <4 x float> %vecinit9, <4 x float> %t4, <4 x i32> <i32 undef, i32 1, i32 2, i32 7>
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ret <4 x float> %vecinit13
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}
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