forked from OSchip/llvm-project
[AArch64][GlobalISel] Legalization and ISel support for load/stores of vectors of pointers.
Loads and store of values with type like <2 x p0> currently don't get imported because SelectionDAG has no knowledge of pointer types. To leverage the existing support for vector load/stores, we can bitcast the value to have s64 element types instead. We do this as a custom legalization. This patch also adds support for general loads of <2 x s64>, and relaxes some type conditions on selecting G_BITCAST. Differential Revision: https://reviews.llvm.org/D60534 llvm-svn: 358221
This commit is contained in:
Amara Emerson
parent
994023a3f1
commit
b956051415
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@ -1658,11 +1658,10 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
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case TargetOpcode::G_BITCAST:
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// Imported SelectionDAG rules can handle every bitcast except those that
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// bitcast from a type to the same type. Ideally, these shouldn't occur
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// but we might not run an optimizer that deletes them.
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if (MRI.getType(I.getOperand(0).getReg()) ==
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MRI.getType(I.getOperand(1).getReg()))
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// but we might not run an optimizer that deletes them. The other exception
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// is bitcasts involving pointer types, as SelectionDAG has no knowledge
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// of them.
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return selectCopy(I, TII, MRI, TRI, RBI);
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return false;
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case TargetOpcode::G_SELECT: {
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if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(1)) {
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@ -21,6 +21,8 @@
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Type.h"
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#define DEBUG_TYPE "aarch64-legalinfo"
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using namespace llvm;
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using namespace LegalizeActions;
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using namespace LegalizeMutations;
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@ -208,13 +210,22 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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// Lower anything left over into G_*EXT and G_LOAD
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.lower();
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auto IsPtrVecPred = [=](const LegalityQuery &Query) {
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const LLT &ValTy = Query.Types[0];
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if (!ValTy.isVector())
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return false;
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const LLT EltTy = ValTy.getElementType();
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return EltTy.isPointer() && EltTy.getAddressSpace() == 0;
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};
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getActionDefinitionsBuilder(G_LOAD)
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.legalForTypesWithMemDesc({{s8, p0, 8, 8},
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{s16, p0, 16, 8},
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{s32, p0, 32, 8},
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{s64, p0, 64, 8},
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{p0, p0, 64, 8},
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{v2s32, p0, 64, 8}})
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{v2s32, p0, 64, 8},
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{v2s64, p0, 128, 8}})
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// These extends are also legal
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.legalForTypesWithMemDesc({{s32, p0, 8, 8},
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{s32, p0, 16, 8}})
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@ -228,7 +239,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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return Query.Types[0].getSizeInBits() != Query.MMODescrs[0].SizeInBits;
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})
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.clampMaxNumElements(0, s32, 2)
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.clampMaxNumElements(0, s64, 1);
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.clampMaxNumElements(0, s64, 1)
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.customIf(IsPtrVecPred);
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getActionDefinitionsBuilder(G_STORE)
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.legalForTypesWithMemDesc({{s8, p0, 8, 8},
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@ -248,7 +260,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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Query.Types[0].getSizeInBits() != Query.MMODescrs[0].SizeInBits;
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})
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.clampMaxNumElements(0, s32, 2)
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.clampMaxNumElements(0, s64, 1);
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.clampMaxNumElements(0, s64, 1)
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.customIf(IsPtrVecPred);
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// Constants
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getActionDefinitionsBuilder(G_CONSTANT)
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@ -357,7 +370,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
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// number of bits but it's what the previous code described and fixing
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// it breaks tests.
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.legalForCartesianProduct({s1, s8, s16, s32, s64, s128, v16s8, v8s8, v4s8,
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v8s16, v4s16, v2s16, v4s32, v2s32, v2s64});
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v8s16, v4s16, v2s16, v4s32, v2s32, v2s64,
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v2p0});
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getActionDefinitionsBuilder(G_VASTART).legalFor({p0});
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@ -541,11 +555,53 @@ bool AArch64LegalizerInfo::legalizeCustom(MachineInstr &MI,
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return false;
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case TargetOpcode::G_VAARG:
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return legalizeVaArg(MI, MRI, MIRBuilder);
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case TargetOpcode::G_LOAD:
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case TargetOpcode::G_STORE:
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return legalizeLoadStore(MI, MRI, MIRBuilder, Observer);
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}
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llvm_unreachable("expected switch to return");
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}
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bool AArch64LegalizerInfo::legalizeLoadStore(
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MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder,
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GISelChangeObserver &Observer) const {
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assert(MI.getOpcode() == TargetOpcode::G_STORE ||
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MI.getOpcode() == TargetOpcode::G_LOAD);
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// Here we just try to handle vector loads/stores where our value type might
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// have pointer elements, which the SelectionDAG importer can't handle. To
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// allow the existing patterns for s64 to fire for p0, we just try to bitcast
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// the value to use s64 types.
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// Custom legalization requires the instruction, if not deleted, must be fully
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// legalized. In order to allow further legalization of the inst, we create
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// a new instruction and erase the existing one.
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unsigned ValReg = MI.getOperand(0).getReg();
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const LLT ValTy = MRI.getType(ValReg);
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if (!ValTy.isVector() || !ValTy.getElementType().isPointer() ||
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ValTy.getElementType().getAddressSpace() != 0) {
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LLVM_DEBUG(dbgs() << "Tried to do custom legalization on wrong load/store");
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return false;
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}
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MIRBuilder.setInstr(MI);
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unsigned PtrSize = ValTy.getElementType().getSizeInBits();
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const LLT NewTy = LLT::vector(ValTy.getNumElements(), PtrSize);
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auto &MMO = **MI.memoperands_begin();
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if (MI.getOpcode() == TargetOpcode::G_STORE) {
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auto Bitcast = MIRBuilder.buildBitcast({NewTy}, {ValReg});
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MIRBuilder.buildStore(Bitcast.getReg(0), MI.getOperand(1).getReg(), MMO);
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} else {
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unsigned NewReg = MRI.createGenericVirtualRegister(NewTy);
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auto NewLoad = MIRBuilder.buildLoad(NewReg, MI.getOperand(1).getReg(), MMO);
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MIRBuilder.buildBitcast({ValReg}, {NewLoad});
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}
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MI.eraseFromParent();
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return true;
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}
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bool AArch64LegalizerInfo::legalizeVaArg(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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@ -34,6 +34,9 @@ public:
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private:
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bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const;
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bool legalizeLoadStore(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder,
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GISelChangeObserver &Observer) const;
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};
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} // End llvm namespace.
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#endif
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@ -158,7 +158,7 @@ end:
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br label %block
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %2:_(<2 x p0>), %1:_(p0) :: (store 16 into `<2 x i16*>* undef`) (in function: vector_of_pointers_insertelement)
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(<2 x p0>) = G_INSERT_VECTOR_ELT %0:_, %3:_(p0), %5:_(s32) (in function: vector_of_pointers_insertelement)
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement
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; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement:
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define void @vector_of_pointers_insertelement() {
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@ -38,12 +38,8 @@ body: |
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; CHECK: liveins: $x0, $x1
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
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; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 8, align 16)
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; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
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; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64)
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; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 8)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[LOAD]](s64), [[LOAD1]](s64)
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; CHECK: G_STORE [[BUILD_VECTOR]](<2 x s64>), [[COPY1]](p0) :: (store 16)
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; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16)
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; CHECK: G_STORE [[LOAD]](<2 x s64>), [[COPY1]](p0) :: (store 16)
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%0:_(p0) = COPY $x0
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%1:_(p0) = COPY $x1
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%2:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16)
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@ -0,0 +1,86 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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define void @store_v2p0(<2 x i8*> %v, <2 x i8*>* %ptr) {
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store <2 x i8*> %v, <2 x i8*>* %ptr
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ret void
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}
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define <2 x i8*> @load_v2p0(<2 x i8*>* %ptr) {
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%v = load <2 x i8*>, <2 x i8*>* %ptr
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ret <2 x i8*> %v
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}
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define void @load_v2p1(<2 x i8*>* %ptr) { ret void }
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...
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---
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name: store_v2p0
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alignment: 2
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.1 (%ir-block.0):
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liveins: $q0, $x0
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; CHECK-LABEL: name: store_v2p0
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; CHECK: liveins: $q0, $x0
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[COPY]](<2 x p0>)
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; CHECK: G_STORE [[BITCAST]](<2 x s64>), [[COPY1]](p0) :: (store 16 into %ir.ptr)
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; CHECK: RET_ReallyLR
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%0:_(<2 x p0>) = COPY $q0
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%1:_(p0) = COPY $x0
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G_STORE %0(<2 x p0>), %1(p0) :: (store 16 into %ir.ptr)
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RET_ReallyLR
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...
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---
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name: load_v2p0
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alignment: 2
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.1 (%ir-block.0):
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liveins: $x0
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; CHECK-LABEL: name: load_v2p0
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.ptr)
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; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD]](<2 x s64>)
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; CHECK: $q0 = COPY [[BITCAST]](<2 x p0>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(p0) = COPY $x0
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%1:_(<2 x p0>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr)
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$q0 = COPY %1(<2 x p0>)
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RET_ReallyLR implicit $q0
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...
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---
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name: load_v2p1
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alignment: 2
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.1 (%ir-block.0):
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liveins: $x0
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; Check that we don't try to bitcast vectors of pointers w/ non-zero addrspaces.
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; CHECK-LABEL: name: load_v2p1
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[LOAD:%[0-9]+]]:_(<2 x p1>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.ptr)
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; CHECK: $q0 = COPY [[LOAD]](<2 x p1>)
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; CHECK: RET_ReallyLR implicit $q0
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%0:_(p0) = COPY $x0
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%1:_(<2 x p1>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr)
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$q0 = COPY %1(<2 x p1>)
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RET_ReallyLR implicit $q0
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...
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@ -0,0 +1,73 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-- -O0 -run-pass=instruction-select -verify-machineinstrs %s -global-isel-abort=1 -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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define void @store_v2p0(<2 x i8*> %v, <2 x i8*>* %ptr) {
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store <2 x i8*> %v, <2 x i8*>* %ptr
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ret void
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}
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define <2 x i8*> @load_v2p0(<2 x i8*>* %ptr) {
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%v = load <2 x i8*>, <2 x i8*>* %ptr
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ret <2 x i8*> %v
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}
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...
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---
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name: store_v2p0
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: gpr }
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- { id: 2, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.1 (%ir-block.0):
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liveins: $q0, $x0
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; CHECK-LABEL: name: store_v2p0
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; CHECK: liveins: $q0, $x0
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; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: STRQui [[COPY]], [[COPY1]], 0 :: (store 16 into %ir.ptr)
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; CHECK: RET_ReallyLR
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%0:fpr(<2 x p0>) = COPY $q0
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%1:gpr(p0) = COPY $x0
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%2:fpr(<2 x s64>) = G_BITCAST %0(<2 x p0>)
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G_STORE %2(<2 x s64>), %1(p0) :: (store 16 into %ir.ptr)
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RET_ReallyLR
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...
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---
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name: load_v2p0
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: fpr }
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- { id: 2, class: fpr }
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machineFunctionInfo: {}
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body: |
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bb.1 (%ir-block.0):
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liveins: $x0
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; CHECK-LABEL: name: load_v2p0
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16 from %ir.ptr)
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; CHECK: $q0 = COPY [[LDRQui]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:gpr(p0) = COPY $x0
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%2:fpr(<2 x s64>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr)
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%1:fpr(<2 x p0>) = G_BITCAST %2(<2 x s64>)
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$q0 = COPY %1(<2 x p0>)
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RET_ReallyLR implicit $q0
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...
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@ -32,6 +32,7 @@
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define void @load_gep_32_s8_fpr(i8* %addr) { ret void }
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define void @load_v2s32(i64 *%addr) { ret void }
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define void @load_v2s64(i64 *%addr) { ret void }
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...
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---
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@ -112,8 +113,8 @@ body: |
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; CHECK-LABEL: name: load_s16_gpr
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
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; CHECK: [[T0:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
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; CHECK: $w0 = COPY [[T0]]
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; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
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; CHECK: $w0 = COPY [[COPY1]]
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%0(p0) = COPY $x0
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%1(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
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%2:gpr(s32) = G_ANYEXT %1
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@ -129,7 +130,7 @@ body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: load_s8_gpr
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; CHECK-LABEL: name: load_s8_gpr_anyext
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1 from %ir.addr)
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; CHECK: $w0 = COPY [[LDRBBui]]
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@ -154,8 +155,8 @@ body: |
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; CHECK-LABEL: name: load_s8_gpr
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; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
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; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1 from %ir.addr)
|
||||
; CHECK: [[T0:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
|
||||
; CHECK: $w0 = COPY [[T0]]
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
|
||||
; CHECK: $w0 = COPY [[COPY1]]
|
||||
%0(p0) = COPY $x0
|
||||
%1(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
|
||||
%2:gpr(s32) = G_ANYEXT %1
|
||||
|
|
@ -256,8 +257,8 @@ body: |
|
|||
; CHECK-LABEL: name: load_gep_64_s16_gpr
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
||||
; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 32 :: (load 2 from %ir.addr)
|
||||
; CHECK: [[T0:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
|
||||
; CHECK: $w0 = COPY [[T0]]
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
|
||||
; CHECK: $w0 = COPY [[COPY1]]
|
||||
%0(p0) = COPY $x0
|
||||
%1(s64) = G_CONSTANT i64 64
|
||||
%2(p0) = G_GEP %0, %1
|
||||
|
|
@ -284,8 +285,8 @@ body: |
|
|||
; CHECK-LABEL: name: load_gep_1_s8_gpr
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
||||
; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 1 :: (load 1 from %ir.addr)
|
||||
; CHECK: [[T0:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
|
||||
; CHECK: $w0 = COPY [[T0]]
|
||||
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
|
||||
; CHECK: $w0 = COPY [[COPY1]]
|
||||
%0(p0) = COPY $x0
|
||||
%1(s64) = G_CONSTANT i64 1
|
||||
%2(p0) = G_GEP %0, %1
|
||||
|
|
@ -506,3 +507,24 @@ body: |
|
|||
%1(<2 x s32>) = G_LOAD %0 :: (load 8 from %ir.addr)
|
||||
$d0 = COPY %1(<2 x s32>)
|
||||
...
|
||||
---
|
||||
name: load_v2s64
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
registers:
|
||||
- { id: 0, class: gpr }
|
||||
- { id: 1, class: fpr }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $x0
|
||||
|
||||
; CHECK-LABEL: name: load_v2s64
|
||||
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
|
||||
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load 16 from %ir.addr)
|
||||
; CHECK: $q0 = COPY [[LDRQui]]
|
||||
%0(p0) = COPY $x0
|
||||
%1(<2 x s64>) = G_LOAD %0 :: (load 16 from %ir.addr)
|
||||
$q0 = COPY %1(<2 x s64>)
|
||||
...
|
||||
|
|
|
|||
Loading…
Reference in New Issue