forked from OSchip/llvm-project
[VE] VE Vector Predicated SDNode, vector add isel and tests
VE Vector Predicated (VVP) SDNodes form an intermediate layer between VE vector instructions and the initial SDNodes. We introduce 'vvp_add' with isel and tests as the first of these VVP nodes. VVP nodes have a mask and explicit vector length operand, which we will make proper use of later. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D91802
This commit is contained in:
Simon Moll
parent
619630f997
commit
b955c7e630
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@ -254,8 +254,17 @@ void VETargetLowering::initSPUActions() {
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}
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void VETargetLowering::initVPUActions() {
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for (MVT LegalVecVT : AllVectorVTs)
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for (MVT LegalVecVT : AllVectorVTs) {
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setOperationAction(ISD::BUILD_VECTOR, LegalVecVT, Custom);
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// Translate all vector instructions with legal element types to VVP_*
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// nodes.
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// TODO We will custom-widen into VVP_* nodes in the future. While we are
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// buildling the infrastructure for this, we only do this for legal vector
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// VTs.
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#define ADD_VVP_OP(VVP_NAME, ISD_NAME) \
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setOperationAction(ISD::ISD_NAME, LegalVecVT, Custom);
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#include "VVPNodes.def"
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}
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}
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SDValue
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@ -846,6 +855,10 @@ const char *VETargetLowering::getTargetNodeName(unsigned Opcode) const {
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TARGET_NODE_CASE(VEC_BROADCAST)
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TARGET_NODE_CASE(RET_FLAG)
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TARGET_NODE_CASE(GLOBAL_BASE_REG)
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// Register the VVP_* SDNodes.
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#define ADD_VVP_OP(VVP_NAME, ...) TARGET_NODE_CASE(VVP_NAME)
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#include "VVPNodes.def"
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}
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#undef TARGET_NODE_CASE
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return nullptr;
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@ -1403,6 +1416,10 @@ SDValue VETargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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return lowerVASTART(Op, DAG);
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case ISD::VAARG:
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return lowerVAARG(Op, DAG);
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#define ADD_BINARY_VVP_OP(VVP_NAME, ISD_NAME) case ISD::ISD_NAME:
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#include "VVPNodes.def"
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return lowerToVVP(Op, DAG);
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}
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}
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/// } Custom Lower
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@ -1665,3 +1682,53 @@ bool VETargetLowering::hasAndNot(SDValue Y) const {
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// It's ok for generic registers.
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return true;
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}
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/// \returns the VVP_* SDNode opcode corresponsing to \p OC.
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static Optional<unsigned> getVVPOpcode(unsigned OC) {
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switch (OC) {
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#define ADD_VVP_OP(VVPNAME, SDNAME) \
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case VEISD::VVPNAME: \
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case ISD::SDNAME: \
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return VEISD::VVPNAME;
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#include "VVPNodes.def"
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}
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return None;
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}
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SDValue VETargetLowering::lowerToVVP(SDValue Op, SelectionDAG &DAG) const {
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// Can we represent this as a VVP node.
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auto OCOpt = getVVPOpcode(Op->getOpcode());
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if (!OCOpt.hasValue())
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return SDValue();
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unsigned VVPOC = OCOpt.getValue();
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// The representative and legalized vector type of this operation.
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EVT OpVecVT = Op.getValueType();
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EVT LegalVecVT = getTypeToTransformTo(*DAG.getContext(), OpVecVT);
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// Materialize the VL parameter.
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SDLoc DL(Op);
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SDValue AVL = DAG.getConstant(OpVecVT.getVectorNumElements(), DL, MVT::i32);
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MVT MaskVT = MVT::v256i1;
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SDValue ConstTrue = DAG.getConstant(1, DL, MVT::i32);
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SDValue Mask = DAG.getNode(VEISD::VEC_BROADCAST, DL, MaskVT,
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ConstTrue); // emit a VEISD::VEC_BROADCAST here.
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// Categories we are interested in.
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bool IsBinaryOp = false;
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switch (VVPOC) {
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#define ADD_BINARY_VVP_OP(VVPNAME, ...) \
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case VEISD::VVPNAME: \
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IsBinaryOp = true; \
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break;
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#include "VVPNodes.def"
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}
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if (IsBinaryOp) {
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assert(LegalVecVT.isSimple());
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return DAG.getNode(VVPOC, DL, LegalVecVT, Op->getOperand(0),
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Op->getOperand(1), Mask, AVL);
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}
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llvm_unreachable("lowerToVVP called for unexpected SDNode.");
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}
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@ -39,6 +39,10 @@ enum NodeType : unsigned {
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CALL, // A call instruction.
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RET_FLAG, // Return with a flag operand.
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GLOBAL_BASE_REG, // Global base reg for PIC.
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// VVP_* nodes.
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#define ADD_VVP_OP(VVP_NAME, ...) VVP_NAME,
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#include "VVPNodes.def"
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};
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}
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@ -120,6 +124,10 @@ public:
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SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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/// } Custom Lower
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/// VVP Lowering {
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SDValue lowerToVVP(SDValue Op, SelectionDAG &DAG) const;
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/// } VVPLowering
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/// Custom DAGCombine {
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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@ -245,6 +245,7 @@ def fplomsbzero : PatLeaf<(fpimm), [{ return (getFpImmVal(N) & 0x80000000)
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== 0; }]>;
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def fplozero : PatLeaf<(fpimm), [{ return (getFpImmVal(N) & 0xffffffff)
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== 0; }]>;
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def nonzero : PatLeaf<(imm), [{ return N->getSExtValue() !=0 ; }]>;
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def CCSIOp : PatLeaf<(cond), [{
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switch (N->get()) {
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@ -2219,6 +2220,22 @@ def : Pat<(i32 (and i32:$val, 0xffff)),
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def : Pat<(i64 (and i64:$val, 0xffffffff)),
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(ANDrm $val, !add(32, 64))>;
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//===----------------------------------------------------------------------===//
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// Vector Instruction Pattern Stuff
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//===----------------------------------------------------------------------===//
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// Custom intermediate ISDs.
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class IsVLVT<int OpIdx> : SDTCisVT<OpIdx,i32>;
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def vec_broadcast : SDNode<"VEISD::VEC_BROADCAST", SDTypeProfile<1, 2,
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[SDTCisVec<0>, IsVLVT<2>]>>;
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// Whether this is an all-true mask (assuming undef-bits above VL are all-true).
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def true_mask : PatLeaf<
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(vec_broadcast (i32 nonzero), (i32 srcvalue))>;
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// Match any broadcast (ignoring VL).
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def any_broadcast : PatFrag<(ops node:$sx),
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(vec_broadcast node:$sx, (i32 srcvalue))>;
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// Vector instructions.
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include "VEInstrVec.td"
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@ -2227,3 +2244,6 @@ include "VEInstrIntrinsicVL.td"
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// Patterns and intermediate SD nodes (VEC_*).
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include "VEInstrPatternsVec.td"
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// Patterns and intermediate SD nodes (VVP_*).
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include "VVPInstrPatternsVec.td"
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@ -15,10 +15,6 @@
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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// Custom intermediate ISDs.
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class IsVLVT<int OpIdx> : SDTCisVT<OpIdx,i32>;
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def vec_broadcast : SDNode<"VEISD::VEC_BROADCAST", SDTypeProfile<1, 2, [SDTCisVec<0>, IsVLVT<2>]>>;
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multiclass vbrd_elem32<ValueType v32, ValueType s32, SDPatternOperator ImmOp, SDNodeXForm ImmCast, int SubRegIdx> {
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// VBRDil
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def : Pat<(v32 (vec_broadcast (s32 ImmOp:$sy), i32:$vl)),
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@ -0,0 +1,43 @@
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//===-------------- VVPInstrInfo.td - VVP_* SDNode patterns ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the VE Vector Predicated SDNodes (VVP SDNodes). VVP
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// SDNodes are an intermediate isel layer between the vector SDNodes emitted by
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// LLVM and the actual VE vector instructions. For example:
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//
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// ADD(x,y) --> VVP_ADD(x,y,mask,evl) --> VADDSWSXrvml(x,y,mask,evl)
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// ^ ^ ^
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// The standard The VVP layer SDNode. The VE vector instruction.
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// SDNode.
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//
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// TODO explain how VVP nodes relate to VP SDNodes once VP ISel is uptream.
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//===----------------------------------------------------------------------===//
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// Binary Operators {
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// BinaryOp(x,y,mask,vl)
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def SDTIntBinOpVVP : SDTypeProfile<1, 4, [ // vp_add, vp_and, etc.
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SDTCisSameAs<0, 1>,
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SDTCisSameAs<0, 2>,
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SDTCisInt<0>,
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SDTCisSameNumEltsAs<0, 3>,
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IsVLVT<4>
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]>;
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// Binary operator commutative pattern.
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class vvp_commutative<SDNode RootOp> :
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PatFrags<
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(ops node:$lhs, node:$rhs, node:$mask, node:$vlen),
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[(RootOp node:$lhs, node:$rhs, node:$mask, node:$vlen),
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(RootOp node:$rhs, node:$lhs, node:$mask, node:$vlen)]>;
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// VVP node definitions.
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def vvp_add : SDNode<"VEISD::VVP_ADD", SDTIntBinOpVVP>;
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def c_vvp_add : vvp_commutative<vvp_add>;
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// } Binary Operators
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@ -0,0 +1,68 @@
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//===----------- VVPInstrPatternsVec.td - VVP_* SDNode patterns -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes how VVP_* SDNodes are lowered to machine instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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// VVP SDNode definitions.
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//
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//===----------------------------------------------------------------------===//
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include "VVPInstrInfo.td"
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multiclass VectorBinaryArith<
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SDPatternOperator OpNode,
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ValueType ScalarVT, ValueType DataVT, ValueType MaskVT,
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string OpBaseName,
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SDPatternOperator ImmOp, SDNodeXForm ImmCast> {
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// No mask.
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def : Pat<(OpNode
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(any_broadcast ScalarVT:$sx),
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DataVT:$vy, (MaskVT true_mask), i32:$avl),
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(!cast<Instruction>(OpBaseName#"rvl")
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ScalarVT:$sx, $vy, $avl)>;
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def : Pat<(OpNode DataVT:$vx, DataVT:$vy, (MaskVT true_mask), i32:$avl),
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(!cast<Instruction>(OpBaseName#"vvl")
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$vx, $vy, $avl)>;
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// Mask.
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def : Pat<(OpNode
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(any_broadcast ScalarVT:$sx),
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DataVT:$vy, MaskVT:$mask, i32:$avl),
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(!cast<Instruction>(OpBaseName#"rvml")
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ScalarVT:$sx, $vy, $mask, $avl)>;
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def : Pat<(OpNode DataVT:$vx, DataVT:$vy, MaskVT:$mask, i32:$avl),
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(!cast<Instruction>(OpBaseName#"vvml")
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$vx, $vy, $mask, $avl)>;
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// TODO We do not specify patterns for the immediate variants here. There
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// will be an immediate folding pass that takes care of switching to the
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// immediate variant where applicable.
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// TODO Fold vvp_select into passthru.
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}
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// Expand both 64bit and 32 bit variant (256 elements)
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multiclass VectorBinaryArith_ShortLong<
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SDPatternOperator OpNode,
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ValueType LongScalarVT, ValueType LongDataVT, string LongOpBaseName,
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ValueType ShortScalarVT, ValueType ShortDataVT, string ShortOpBaseName> {
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defm : VectorBinaryArith<OpNode,
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LongScalarVT, LongDataVT, v256i1,
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LongOpBaseName, simm7, LO7>;
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defm : VectorBinaryArith<OpNode,
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ShortScalarVT, ShortDataVT, v256i1,
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ShortOpBaseName, simm7, LO7>;
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}
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defm : VectorBinaryArith_ShortLong<c_vvp_add,
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i64, v256i64, "VADDSL",
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i32, v256i32, "VADDSWSX">;
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@ -0,0 +1,32 @@
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//===-- VVPNodes.def - Lists & properties of VE Vector Predication Nodes --===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines all VVP_* SDNodes and their properties
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//
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//===----------------------------------------------------------------------===//
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/// ADD_VVP_OP(VVPNAME,SDNAME)
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/// \p VVPName is a VVP SDNode operator.
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/// \p SDNAME is the generic SD opcode corresponding to \p VVPName.
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#ifndef ADD_VVP_OP
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#define ADD_VVP_OP(X, Y)
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#endif
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/// ADD_BINARY_VVP_OP(VVPNAME,SDNAME)
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/// \p VVPName is a VVP Binary operator.
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/// \p SDNAME is the generic SD opcode corresponding to \p VVPName.
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#ifndef ADD_BINARY_VVP_OP
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#define ADD_BINARY_VVP_OP(X,Y) ADD_VVP_OP(X,Y)
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#endif
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// Integer arithmetic.
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ADD_BINARY_VVP_OP(VVP_ADD,ADD)
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#undef ADD_BINARY_VVP_OP
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#undef ADD_VVP_OP
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@ -0,0 +1,132 @@
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; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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; <256 x i32>
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; Function Attrs: nounwind
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define fastcc <256 x i32> @add_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
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; CHECK-LABEL: add_vv_v256i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vadds.w.sx %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%z = add <256 x i32> %x, %y
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ret <256 x i32> %z
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}
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; Function Attrs: nounwind
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define fastcc <256 x i32> @add_sv_v256i32(i32 %x, <256 x i32> %y) {
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; CHECK-LABEL: add_sv_v256i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vadds.w.sx %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%xins = insertelement <256 x i32> undef, i32 %x, i32 0
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%vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
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%z = add <256 x i32> %vx, %y
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ret <256 x i32> %z
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}
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; Function Attrs: nounwind
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define fastcc <256 x i32> @add_vs_v256i32(<256 x i32> %x, i32 %y) {
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; CHECK-LABEL: add_vs_v256i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vadds.w.sx %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%yins = insertelement <256 x i32> undef, i32 %y, i32 0
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%vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
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%z = add <256 x i32> %x, %vy
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ret <256 x i32> %z
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}
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; <256 x i64>
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; Function Attrs: nounwind
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define fastcc <256 x i64> @add_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
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; CHECK-LABEL: add_vv_v256i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: vadds.l %v0, %v0, %v1
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; CHECK-NEXT: b.l.t (, %s10)
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%z = add <256 x i64> %x, %y
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ret <256 x i64> %z
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}
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; Function Attrs: nounwind
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define fastcc <256 x i64> @add_sv_v256i64(i64 %x, <256 x i64> %y) {
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; CHECK-LABEL: add_sv_v256i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vadds.l %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%xins = insertelement <256 x i64> undef, i64 %x, i32 0
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%vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
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%z = add <256 x i64> %vx, %y
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ret <256 x i64> %z
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}
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; Function Attrs: nounwind
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define fastcc <256 x i64> @add_vs_v256i64(<256 x i64> %x, i64 %y) {
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; CHECK-LABEL: add_vs_v256i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vadds.l %v0, %s0, %v0
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; CHECK-NEXT: b.l.t (, %s10)
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%yins = insertelement <256 x i64> undef, i64 %y, i32 0
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%vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
|
||||
%z = add <256 x i64> %x, %vy
|
||||
ret <256 x i64> %z
|
||||
}
|
||||
|
||||
; <128 x i64>
|
||||
; We expect this to be widened.
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define fastcc <128 x i64> @add_vv_v128i64(<128 x i64> %x, <128 x i64> %y) {
|
||||
; CHECK-LABEL: add_vv_v128i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: lea %s0, 256
|
||||
; CHECK-NEXT: lvl %s0
|
||||
; CHECK-NEXT: vadds.l %v0, %v0, %v1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%z = add <128 x i64> %x, %y
|
||||
ret <128 x i64> %z
|
||||
}
|
||||
|
||||
; <256 x i16>
|
||||
; We expect promotion.
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define fastcc <256 x i16> @add_vv_v256i16(<256 x i16> %x, <256 x i16> %y) {
|
||||
; CHECK-LABEL: add_vv_v256i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: lea %s0, 256
|
||||
; CHECK-NEXT: lvl %s0
|
||||
; CHECK-NEXT: vadds.w.sx %v0, %v0, %v1
|
||||
; CHECK-NEXT: b.l.t (, %s10)
|
||||
%z = add <256 x i16> %x, %y
|
||||
ret <256 x i16> %z
|
||||
}
|
||||
|
||||
; <128 x i16>
|
||||
; We expect this to be scalarized (for now).
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define fastcc <128 x i16> @add_vv_v128i16(<128 x i16> %x, <128 x i16> %y) {
|
||||
; CHECK-LABEL: add_vv_v128i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NOT: vadd
|
||||
%z = add <128 x i16> %x, %y
|
||||
ret <128 x i16> %z
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue