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AArch64: support f16 extend/trunc operations. 

llvm-svn: 213375
This commit is contained in:
Tim Northover 2014-07-18 13:01:31 +00:00
parent 871de902af
commit b94f0859e5
2 changed files with 37 additions and 0 deletions
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1
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -305,6 +305,7 @@ AArch64TargetLowering::AArch64TargetLowering(TargetMachine &TM)
// AArch64 does not have floating-point extending loads, i1 sign-extending
// load, floating-point truncating stores, or v2i32->v2i16 truncating store.
setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);

36
llvm/test/CodeGen/AArch64/half.ll
View File

@ -24,3 +24,39 @@ define void @test_bitcast_to_half(half* %addr, i16 %in) {
store half %val_fp, half* %addr
ret void
}
define float @test_extend32(half* %addr) {
; CHECK-LABEL: test_extend32:
; CHECK: fcvt {{s[0-9]+}}, {{h[0-9]+}}
%val16 = load half* %addr
%val32 = fpext half %val16 to float
ret float %val32
}
define double @test_extend64(half* %addr) {
; CHECK-LABEL: test_extend64:
; CHECK: fcvt {{d[0-9]+}}, {{h[0-9]+}}
%val16 = load half* %addr
%val32 = fpext half %val16 to double
ret double %val32
}
define void @test_trunc32(float %in, half* %addr) {
; CHECK-LABEL: test_trunc32:
; CHECK: fcvt {{h[0-9]+}}, {{s[0-9]+}}
%val16 = fptrunc float %in to half
store half %val16, half* %addr
ret void
}
define void @test_trunc64(double %in, half* %addr) {
; CHECK-LABEL: test_trunc64:
; CHECK: fcvt {{h[0-9]+}}, {{d[0-9]+}}
%val16 = fptrunc double %in to half
store half %val16, half* %addr
ret void
}