From b941f5dc5f36daf6fac61b5bb2faf9e461a6cc91 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Mon, 12 Feb 2018 15:57:00 +0000
Subject: [PATCH] [X86] Tag CET-IBT instruction scheduler classes

llvm-svn: 324898
---
 llvm/lib/Target/X86/X86InstrSystem.td | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/X86/X86InstrSystem.td b/llvm/lib/Target/X86/X86InstrSystem.td
index 1d1b9698daee..5e7c8654b0de 100644
--- a/llvm/lib/Target/X86/X86InstrSystem.td
+++ b/llvm/lib/Target/X86/X86InstrSystem.td
@@ -536,10 +536,10 @@ let SchedRW = [WriteSystem], Predicates = [HasSHSTK]  in{
   } // Defs SSP
 } // SchedRW && HasSHSTK
 
-let Predicates = [HasIBT]  in {
+let SchedRW = [WriteSystem], Predicates = [HasIBT]  in {
     def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS;
     def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS;
-} // HasIBT
+} // SchedRW && HasIBT
 
 //===----------------------------------------------------------------------===//
 // XSAVE instructions