forked from OSchip/llvm-project
[X86] Add back _mask, _maskz, and _mask3 builtins for some 512-bit fmadd/fmsub/fmaddsub/fmsubadd builtins.
Summary: We recently switch to using a selects in the intrinsics header files for FMA instructions. But the 512-bit versions support flavors with rounding mode which must be an Integer Constant Expression. This has forced those intrinsics to be implemented as macros. As it stands now the mask and mask3 intrinsics evaluate one of their macro arguments twice. If that argument itself is another intrinsic macro, we can end up over expanding macros. Or if its something we can CSE later it would show up multiple times when it shouldn't. I tried adding __extension__ around the macro and making it an expression statement and declaring a local variable. But whatever name you choose for the local variable can never be used as the name of an input to the macro in user code. If that happens you would end up with the same name on the LHS and RHS of an assignment after expansion. We might be safe if we use __ in front of the variable names because those names are reserved and user code shouldn't use that, but I wasn't sure I wanted to make that claim. The other option which I've chosen here, is to add back _mask, _maskz, and _mask3 flavors of the builtin which we will expand in CGBuiltin.cpp to replicate the argument as needed and insert any fneg needed on the third operand to make a subtract. The _maskz isn't truly necessary if we have an unmasked version or if we use the masked version with a -1 mask and wrap a select around it. But I've chosen to make things more uniform. I separated out the scalar builtin handling to avoid too many things going on in EmitX86FMAExpr. It was different enough due to the extract and insert that the minor duplication of the CreateCall was probably worth it. Reviewers: tkrupa, RKSimon, spatel, GBuella Reviewed By: tkrupa Subscribers: cfe-commits Differential Revision: https://reviews.llvm.org/D47724 llvm-svn: 334159
This commit is contained in:
Craig Topper
parent
67af99235f
commit
b92c77d176
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@ -731,10 +731,22 @@ TARGET_BUILTIN(__builtin_ia32_vfmaddpd256, "V4dV4dV4dV4d", "nc", "fma|fma4")
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TARGET_BUILTIN(__builtin_ia32_vfmaddsubps256, "V8fV8fV8fV8f", "nc", "fma|fma4")
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TARGET_BUILTIN(__builtin_ia32_vfmaddsubpd256, "V4dV4dV4dV4d", "nc", "fma|fma4")
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TARGET_BUILTIN(__builtin_ia32_vfmaddpd512, "V8dV8dV8dV8dIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmaddps512, "V16fV16fV16fV16fIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmaddsubpd512, "V8dV8dV8dV8dIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmaddsubps512, "V16fV16fV16fV16fIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmaddpd512_mask, "V8dV8dV8dV8dUcIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmaddpd512_maskz, "V8dV8dV8dV8dUcIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmaddpd512_mask3, "V8dV8dV8dV8dUcIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmsubpd512_mask3, "V8dV8dV8dV8dUcIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmaddps512_mask, "V16fV16fV16fV16fUsIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmaddps512_maskz, "V16fV16fV16fV16fUsIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmaddps512_mask3, "V16fV16fV16fV16fUsIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmsubps512_mask3, "V16fV16fV16fV16fUsIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmaddsubpd512_mask, "V8dV8dV8dV8dUcIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmaddsubpd512_maskz, "V8dV8dV8dV8dUcIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmaddsubpd512_mask3, "V8dV8dV8dV8dUcIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmsubaddpd512_mask3, "V8dV8dV8dV8dUcIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmaddsubps512_mask, "V16fV16fV16fV16fUsIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmaddsubps512_maskz, "V16fV16fV16fV16fUsIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmaddsubps512_mask3, "V16fV16fV16fV16fUsIi", "nc", "avx512f")
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TARGET_BUILTIN(__builtin_ia32_vfmsubaddps512_mask3, "V16fV16fV16fV16fUsIi", "nc", "avx512f")
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// XOP
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TARGET_BUILTIN(__builtin_ia32_vpmacssww, "V8sV8sV8sV8s", "nc", "xop")
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@ -8555,79 +8555,110 @@ static Value *EmitX86MinMax(CodeGenFunction &CGF, ICmpInst::Predicate Pred,
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// Lowers X86 FMA intrinsics to IR.
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static Value *EmitX86FMAExpr(CodeGenFunction &CGF, ArrayRef<Value *> Ops,
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unsigned BuiltinID) {
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unsigned BuiltinID, bool IsAddSub) {
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bool IsAddSub = false;
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bool IsScalar = false;
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// 4 operands always means rounding mode without a mask here.
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bool IsRound = Ops.size() == 4;
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Intrinsic::ID ID;
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bool Subtract = false;
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Intrinsic::ID IID = Intrinsic::not_intrinsic;
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switch (BuiltinID) {
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default: break;
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case clang::X86::BI__builtin_ia32_vfmaddss3: IsScalar = true; break;
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case clang::X86::BI__builtin_ia32_vfmaddsd3: IsScalar = true; break;
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case clang::X86::BI__builtin_ia32_vfmaddps512:
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ID = llvm::Intrinsic::x86_avx512_vfmadd_ps_512; break;
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case clang::X86::BI__builtin_ia32_vfmaddpd512:
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ID = llvm::Intrinsic::x86_avx512_vfmadd_pd_512; break;
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case clang::X86::BI__builtin_ia32_vfmaddsubps: IsAddSub = true; break;
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case clang::X86::BI__builtin_ia32_vfmaddsubpd: IsAddSub = true; break;
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case clang::X86::BI__builtin_ia32_vfmaddsubps256: IsAddSub = true; break;
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case clang::X86::BI__builtin_ia32_vfmaddsubpd256: IsAddSub = true; break;
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case clang::X86::BI__builtin_ia32_vfmaddsubps512: {
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ID = llvm::Intrinsic::x86_avx512_vfmaddsub_ps_512;
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IsAddSub = true;
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case clang::X86::BI__builtin_ia32_vfmsubps512_mask3:
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Subtract = true;
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LLVM_FALLTHROUGH;
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case clang::X86::BI__builtin_ia32_vfmaddps512_mask:
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case clang::X86::BI__builtin_ia32_vfmaddps512_maskz:
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case clang::X86::BI__builtin_ia32_vfmaddps512_mask3:
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IID = llvm::Intrinsic::x86_avx512_vfmadd_ps_512; break;
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case clang::X86::BI__builtin_ia32_vfmsubpd512_mask3:
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Subtract = true;
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LLVM_FALLTHROUGH;
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case clang::X86::BI__builtin_ia32_vfmaddpd512_mask:
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case clang::X86::BI__builtin_ia32_vfmaddpd512_maskz:
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case clang::X86::BI__builtin_ia32_vfmaddpd512_mask3:
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IID = llvm::Intrinsic::x86_avx512_vfmadd_pd_512; break;
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case clang::X86::BI__builtin_ia32_vfmsubaddps512_mask3:
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Subtract = true;
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LLVM_FALLTHROUGH;
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case clang::X86::BI__builtin_ia32_vfmaddsubps512_mask:
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case clang::X86::BI__builtin_ia32_vfmaddsubps512_maskz:
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case clang::X86::BI__builtin_ia32_vfmaddsubps512_mask3:
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IID = llvm::Intrinsic::x86_avx512_vfmaddsub_ps_512;
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break;
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}
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case clang::X86::BI__builtin_ia32_vfmaddsubpd512: {
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ID = llvm::Intrinsic::x86_avx512_vfmaddsub_pd_512;
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IsAddSub = true;
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case clang::X86::BI__builtin_ia32_vfmsubaddpd512_mask3:
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Subtract = true;
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LLVM_FALLTHROUGH;
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case clang::X86::BI__builtin_ia32_vfmaddsubpd512_mask:
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case clang::X86::BI__builtin_ia32_vfmaddsubpd512_maskz:
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case clang::X86::BI__builtin_ia32_vfmaddsubpd512_mask3:
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IID = llvm::Intrinsic::x86_avx512_vfmaddsub_pd_512;
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break;
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}
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}
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// Only handle in case of _MM_FROUND_CUR_DIRECTION/4 (no rounding).
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if (IsRound) {
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Function *Intr = CGF.CGM.getIntrinsic(ID);
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if (cast<llvm::ConstantInt>(Ops[3])->getZExtValue() != (uint64_t)4)
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return CGF.Builder.CreateCall(Intr, Ops);
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}
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Value *A = Ops[0];
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Value *B = Ops[1];
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Value *C = Ops[2];
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if (IsScalar) {
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A = CGF.Builder.CreateExtractElement(A, (uint64_t)0);
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B = CGF.Builder.CreateExtractElement(B, (uint64_t)0);
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C = CGF.Builder.CreateExtractElement(C, (uint64_t)0);
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}
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if (Subtract)
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C = CGF.Builder.CreateFNeg(C);
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llvm::Type *Ty = A->getType();
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Function *FMA = CGF.CGM.getIntrinsic(Intrinsic::fma, Ty);
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Value *Res = CGF.Builder.CreateCall(FMA, {A, B, C} );
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Value *Res;
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if (IsScalar)
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return CGF.Builder.CreateInsertElement(Ops[0], Res, (uint64_t)0);
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// Only handle in case of _MM_FROUND_CUR_DIRECTION/4 (no rounding).
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if (IID != Intrinsic::not_intrinsic &&
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cast<llvm::ConstantInt>(Ops.back())->getZExtValue() != (uint64_t)4) {
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Function *Intr = CGF.CGM.getIntrinsic(IID);
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Res = CGF.Builder.CreateCall(Intr, {A, B, C, Ops.back() });
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} else {
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llvm::Type *Ty = A->getType();
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Function *FMA = CGF.CGM.getIntrinsic(Intrinsic::fma, Ty);
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Res = CGF.Builder.CreateCall(FMA, {A, B, C} );
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if (IsAddSub) {
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// Negate even elts in C using a mask.
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unsigned NumElts = Ty->getVectorNumElements();
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SmallVector<Constant *, 16> NMask;
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Constant *Zero = ConstantInt::get(CGF.Builder.getInt1Ty(), 0);
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Constant *One = ConstantInt::get(CGF.Builder.getInt1Ty(), 1);
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for (unsigned i = 0; i < NumElts; ++i) {
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NMask.push_back(i % 2 == 0 ? One : Zero);
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if (IsAddSub) {
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// Negate even elts in C using a mask.
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unsigned NumElts = Ty->getVectorNumElements();
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SmallVector<Constant *, 16> NMask;
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Constant *Zero = ConstantInt::get(CGF.Builder.getInt1Ty(), 0);
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Constant *One = ConstantInt::get(CGF.Builder.getInt1Ty(), 1);
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for (unsigned i = 0; i < NumElts; ++i) {
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NMask.push_back(i % 2 == 0 ? One : Zero);
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}
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Value *NegMask = ConstantVector::get(NMask);
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Value *NegC = CGF.Builder.CreateFNeg(C);
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Value *FMSub = CGF.Builder.CreateCall(FMA, {A, B, NegC} );
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Res = CGF.Builder.CreateSelect(NegMask, FMSub, Res);
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}
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Value *NegMask = ConstantVector::get(NMask);
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Value *NegC = CGF.Builder.CreateFNeg(C);
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Value *FMSub = CGF.Builder.CreateCall(FMA, {A, B, NegC} );
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Res = CGF.Builder.CreateSelect(NegMask, FMSub, Res);
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}
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// Handle any required masking.
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Value *MaskFalseVal = nullptr;
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switch (BuiltinID) {
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case clang::X86::BI__builtin_ia32_vfmaddps512_mask:
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case clang::X86::BI__builtin_ia32_vfmaddpd512_mask:
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case clang::X86::BI__builtin_ia32_vfmaddsubps512_mask:
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case clang::X86::BI__builtin_ia32_vfmaddsubpd512_mask:
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MaskFalseVal = Ops[0];
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break;
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case clang::X86::BI__builtin_ia32_vfmaddps512_maskz:
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case clang::X86::BI__builtin_ia32_vfmaddpd512_maskz:
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case clang::X86::BI__builtin_ia32_vfmaddsubps512_maskz:
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case clang::X86::BI__builtin_ia32_vfmaddsubpd512_maskz:
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MaskFalseVal = Constant::getNullValue(Ops[0]->getType());
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break;
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case clang::X86::BI__builtin_ia32_vfmsubps512_mask3:
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case clang::X86::BI__builtin_ia32_vfmaddps512_mask3:
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case clang::X86::BI__builtin_ia32_vfmsubpd512_mask3:
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case clang::X86::BI__builtin_ia32_vfmaddpd512_mask3:
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case clang::X86::BI__builtin_ia32_vfmsubaddps512_mask3:
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case clang::X86::BI__builtin_ia32_vfmaddsubps512_mask3:
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case clang::X86::BI__builtin_ia32_vfmsubaddpd512_mask3:
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case clang::X86::BI__builtin_ia32_vfmaddsubpd512_mask3:
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MaskFalseVal = Ops[2];
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break;
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}
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if (MaskFalseVal)
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return EmitX86Select(CGF, Ops[3], Res, MaskFalseVal);
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return Res;
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}
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@ -9046,20 +9077,40 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
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return EmitX86ConvertToMask(*this, Ops[0]);
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case X86::BI__builtin_ia32_vfmaddss3:
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case X86::BI__builtin_ia32_vfmaddsd3:
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case X86::BI__builtin_ia32_vfmaddsd3: {
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Value *A = Builder.CreateExtractElement(Ops[0], (uint64_t)0);
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Value *B = Builder.CreateExtractElement(Ops[1], (uint64_t)0);
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Value *C = Builder.CreateExtractElement(Ops[2], (uint64_t)0);
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Function *FMA = CGM.getIntrinsic(Intrinsic::fma, A->getType());
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Value *Res = Builder.CreateCall(FMA, {A, B, C} );
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return Builder.CreateInsertElement(Ops[0], Res, (uint64_t)0);
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}
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case X86::BI__builtin_ia32_vfmaddps:
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case X86::BI__builtin_ia32_vfmaddpd:
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case X86::BI__builtin_ia32_vfmaddps256:
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case X86::BI__builtin_ia32_vfmaddpd256:
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case X86::BI__builtin_ia32_vfmaddps512:
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case X86::BI__builtin_ia32_vfmaddpd512:
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case X86::BI__builtin_ia32_vfmaddps512_mask:
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case X86::BI__builtin_ia32_vfmaddps512_maskz:
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case X86::BI__builtin_ia32_vfmaddps512_mask3:
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case X86::BI__builtin_ia32_vfmsubps512_mask3:
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case X86::BI__builtin_ia32_vfmaddpd512_mask:
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case X86::BI__builtin_ia32_vfmaddpd512_maskz:
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case X86::BI__builtin_ia32_vfmaddpd512_mask3:
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case X86::BI__builtin_ia32_vfmsubpd512_mask3:
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return EmitX86FMAExpr(*this, Ops, BuiltinID, /*IsAddSub*/false);
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case X86::BI__builtin_ia32_vfmaddsubps:
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case X86::BI__builtin_ia32_vfmaddsubpd:
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case X86::BI__builtin_ia32_vfmaddsubps256:
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case X86::BI__builtin_ia32_vfmaddsubpd256:
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case X86::BI__builtin_ia32_vfmaddsubps512:
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case X86::BI__builtin_ia32_vfmaddsubpd512:
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return EmitX86FMAExpr(*this, Ops, BuiltinID);
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case X86::BI__builtin_ia32_vfmaddsubps512_mask:
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case X86::BI__builtin_ia32_vfmaddsubps512_maskz:
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case X86::BI__builtin_ia32_vfmaddsubps512_mask3:
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case X86::BI__builtin_ia32_vfmsubaddps512_mask3:
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case X86::BI__builtin_ia32_vfmaddsubpd512_mask:
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case X86::BI__builtin_ia32_vfmaddsubpd512_maskz:
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case X86::BI__builtin_ia32_vfmaddsubpd512_mask3:
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case X86::BI__builtin_ia32_vfmsubaddpd512_mask3:
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return EmitX86FMAExpr(*this, Ops, BuiltinID, /*IsAddSub*/true);
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case X86::BI__builtin_ia32_movdqa32store128_mask:
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case X86::BI__builtin_ia32_movdqa64store128_mask:
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File diff suppressed because it is too large
Load Diff
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@ -2340,10 +2340,6 @@ bool Sema::CheckX86BuiltinRoundingOrSAE(unsigned BuiltinID, CallExpr *TheCall) {
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case X86::BI__builtin_ia32_cvtuqq2ps512_mask:
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case X86::BI__builtin_ia32_sqrtpd512_mask:
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case X86::BI__builtin_ia32_sqrtps512_mask:
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case X86::BI__builtin_ia32_vfmaddpd512:
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case X86::BI__builtin_ia32_vfmaddps512:
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case X86::BI__builtin_ia32_vfmaddsubpd512:
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case X86::BI__builtin_ia32_vfmaddsubps512:
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ArgNum = 3;
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HasRC = true;
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break;
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@ -2378,6 +2374,22 @@ bool Sema::CheckX86BuiltinRoundingOrSAE(unsigned BuiltinID, CallExpr *TheCall) {
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case X86::BI__builtin_ia32_vfmaddss3_mask:
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case X86::BI__builtin_ia32_vfmaddss3_maskz:
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case X86::BI__builtin_ia32_vfmaddss3_mask3:
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case X86::BI__builtin_ia32_vfmaddpd512_mask:
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case X86::BI__builtin_ia32_vfmaddpd512_maskz:
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case X86::BI__builtin_ia32_vfmaddpd512_mask3:
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case X86::BI__builtin_ia32_vfmsubpd512_mask3:
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case X86::BI__builtin_ia32_vfmaddps512_mask:
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case X86::BI__builtin_ia32_vfmaddps512_maskz:
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case X86::BI__builtin_ia32_vfmaddps512_mask3:
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case X86::BI__builtin_ia32_vfmsubps512_mask3:
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case X86::BI__builtin_ia32_vfmaddsubpd512_mask:
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case X86::BI__builtin_ia32_vfmaddsubpd512_maskz:
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case X86::BI__builtin_ia32_vfmaddsubpd512_mask3:
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case X86::BI__builtin_ia32_vfmsubaddpd512_mask3:
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case X86::BI__builtin_ia32_vfmaddsubps512_mask:
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case X86::BI__builtin_ia32_vfmaddsubps512_maskz:
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case X86::BI__builtin_ia32_vfmaddsubps512_mask3:
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case X86::BI__builtin_ia32_vfmsubaddps512_mask3:
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ArgNum = 4;
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HasRC = true;
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break;
|
||||
|
|
|
|||
|
|
@ -461,7 +461,7 @@ __m512d test_mm512_maskz_fmadd_round_pd(__mmask8 __U, __m512d __A, __m512d __B,
|
|||
// CHECK-LABEL: @test_mm512_maskz_fmadd_round_pd
|
||||
// CHECK: @llvm.x86.avx512.vfmadd.pd.512
|
||||
// CHECK: bitcast i8 %{{.*}} to <8 x i1>
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer
|
||||
return _mm512_maskz_fmadd_round_pd(__U, __A, __B, __C, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
}
|
||||
__m512d test_mm512_fmsub_round_pd(__m512d __A, __m512d __B, __m512d __C) {
|
||||
|
|
@ -483,7 +483,7 @@ __m512d test_mm512_maskz_fmsub_round_pd(__mmask8 __U, __m512d __A, __m512d __B,
|
|||
// CHECK: fsub <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>
|
||||
// CHECK: @llvm.x86.avx512.vfmadd.pd.512
|
||||
// CHECK: bitcast i8 %{{.*}} to <8 x i1>
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer
|
||||
return _mm512_maskz_fmsub_round_pd(__U, __A, __B, __C, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
}
|
||||
__m512d test_mm512_fnmadd_round_pd(__m512d __A, __m512d __B, __m512d __C) {
|
||||
|
|
@ -505,7 +505,7 @@ __m512d test_mm512_maskz_fnmadd_round_pd(__mmask8 __U, __m512d __A, __m512d __B,
|
|||
// CHECK: fsub <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>
|
||||
// CHECK: @llvm.x86.avx512.vfmadd.pd.512
|
||||
// CHECK: bitcast i8 %{{.*}} to <8 x i1>
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer
|
||||
return _mm512_maskz_fnmadd_round_pd(__U, __A, __B, __C, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
}
|
||||
__m512d test_mm512_fnmsub_round_pd(__m512d __A, __m512d __B, __m512d __C) {
|
||||
|
|
@ -521,7 +521,7 @@ __m512d test_mm512_maskz_fnmsub_round_pd(__mmask8 __U, __m512d __A, __m512d __B,
|
|||
// CHECK: fsub <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>
|
||||
// CHECK: @llvm.x86.avx512.vfmadd.pd.512
|
||||
// CHECK: bitcast i8 %{{.*}} to <8 x i1>
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer
|
||||
return _mm512_maskz_fnmsub_round_pd(__U, __A, __B, __C, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
}
|
||||
__m512d test_mm512_fmadd_pd(__m512d __A, __m512d __B, __m512d __C) {
|
||||
|
|
@ -547,7 +547,7 @@ __m512d test_mm512_maskz_fmadd_pd(__mmask8 __U, __m512d __A, __m512d __B, __m512
|
|||
// CHECK-LABEL: @test_mm512_maskz_fmadd_pd
|
||||
// CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}})
|
||||
// CHECK: bitcast i8 %{{.*}} to <8 x i1>
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer
|
||||
return _mm512_maskz_fmadd_pd(__U, __A, __B, __C);
|
||||
}
|
||||
__m512d test_mm512_fmsub_pd(__m512d __A, __m512d __B, __m512d __C) {
|
||||
|
|
@ -569,7 +569,7 @@ __m512d test_mm512_maskz_fmsub_pd(__mmask8 __U, __m512d __A, __m512d __B, __m512
|
|||
// CHECK: fsub <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %{{.*}}
|
||||
// CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}})
|
||||
// CHECK: bitcast i8 %{{.*}} to <8 x i1>
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer
|
||||
return _mm512_maskz_fmsub_pd(__U, __A, __B, __C);
|
||||
}
|
||||
__m512d test_mm512_fnmadd_pd(__m512d __A, __m512d __B, __m512d __C) {
|
||||
|
|
@ -591,7 +591,7 @@ __m512d test_mm512_maskz_fnmadd_pd(__mmask8 __U, __m512d __A, __m512d __B, __m51
|
|||
// CHECK: fsub <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %{{.*}}
|
||||
// CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}})
|
||||
// CHECK: bitcast i8 %{{.*}} to <8 x i1>
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer
|
||||
return _mm512_maskz_fnmadd_pd(__U, __A, __B, __C);
|
||||
}
|
||||
__m512d test_mm512_fnmsub_pd(__m512d __A, __m512d __B, __m512d __C) {
|
||||
|
|
@ -607,7 +607,7 @@ __m512d test_mm512_maskz_fnmsub_pd(__mmask8 __U, __m512d __A, __m512d __B, __m51
|
|||
// CHECK: fsub <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %{{.*}}
|
||||
// CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}})
|
||||
// CHECK: bitcast i8 %{{.*}} to <8 x i1>
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer
|
||||
return _mm512_maskz_fnmsub_pd(__U, __A, __B, __C);
|
||||
}
|
||||
__m512 test_mm512_fmadd_round_ps(__m512 __A, __m512 __B, __m512 __C) {
|
||||
|
|
@ -633,7 +633,7 @@ __m512 test_mm512_maskz_fmadd_round_ps(__mmask16 __U, __m512 __A, __m512 __B, __
|
|||
// CHECK-LABEL: @test_mm512_maskz_fmadd_round_ps
|
||||
// CHECK: @llvm.x86.avx512.vfmadd.ps.512
|
||||
// CHECK: bitcast i16 %{{.*}} to <16 x i1>
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer
|
||||
return _mm512_maskz_fmadd_round_ps(__U, __A, __B, __C, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
}
|
||||
__m512 test_mm512_fmsub_round_ps(__m512 __A, __m512 __B, __m512 __C) {
|
||||
|
|
@ -655,7 +655,7 @@ __m512 test_mm512_maskz_fmsub_round_ps(__mmask16 __U, __m512 __A, __m512 __B, __
|
|||
// CHECK: fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
|
||||
// CHECK: @llvm.x86.avx512.vfmadd.ps.512
|
||||
// CHECK: bitcast i16 %{{.*}} to <16 x i1>
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer
|
||||
return _mm512_maskz_fmsub_round_ps(__U, __A, __B, __C, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
}
|
||||
__m512 test_mm512_fnmadd_round_ps(__m512 __A, __m512 __B, __m512 __C) {
|
||||
|
|
@ -677,7 +677,7 @@ __m512 test_mm512_maskz_fnmadd_round_ps(__mmask16 __U, __m512 __A, __m512 __B, _
|
|||
// CHECK: fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
|
||||
// CHECK: @llvm.x86.avx512.vfmadd.ps.512
|
||||
// CHECK: bitcast i16 %{{.*}} to <16 x i1>
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer
|
||||
return _mm512_maskz_fnmadd_round_ps(__U, __A, __B, __C, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
}
|
||||
__m512 test_mm512_fnmsub_round_ps(__m512 __A, __m512 __B, __m512 __C) {
|
||||
|
|
@ -693,7 +693,7 @@ __m512 test_mm512_maskz_fnmsub_round_ps(__mmask16 __U, __m512 __A, __m512 __B, _
|
|||
// CHECK: fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
|
||||
// CHECK: @llvm.x86.avx512.vfmadd.ps.512
|
||||
// CHECK: bitcast i16 %{{.*}} to <16 x i1>
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer
|
||||
return _mm512_maskz_fnmsub_round_ps(__U, __A, __B, __C, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
}
|
||||
__m512 test_mm512_fmadd_ps(__m512 __A, __m512 __B, __m512 __C) {
|
||||
|
|
@ -717,7 +717,7 @@ __m512 test_mm512_maskz_fmadd_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512 _
|
|||
// CHECK-LABEL: @test_mm512_maskz_fmadd_ps
|
||||
// CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}})
|
||||
// CHECK: bitcast i16 %{{.*}} to <16 x i1>
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer
|
||||
return _mm512_maskz_fmadd_ps(__U, __A, __B, __C);
|
||||
}
|
||||
__m512 test_mm512_fmsub_ps(__m512 __A, __m512 __B, __m512 __C) {
|
||||
|
|
@ -739,7 +739,7 @@ __m512 test_mm512_maskz_fmsub_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512 _
|
|||
// CHECK: fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
|
||||
// CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}})
|
||||
// CHECK: bitcast i16 %{{.*}} to <16 x i1>
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer
|
||||
return _mm512_maskz_fmsub_ps(__U, __A, __B, __C);
|
||||
}
|
||||
__m512 test_mm512_fnmadd_ps(__m512 __A, __m512 __B, __m512 __C) {
|
||||
|
|
@ -761,7 +761,7 @@ __m512 test_mm512_maskz_fnmadd_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512
|
|||
// CHECK: fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
|
||||
// CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}})
|
||||
// CHECK: bitcast i16 %{{.*}} to <16 x i1>
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer
|
||||
return _mm512_maskz_fnmadd_ps(__U, __A, __B, __C);
|
||||
}
|
||||
__m512 test_mm512_fnmsub_ps(__m512 __A, __m512 __B, __m512 __C) {
|
||||
|
|
@ -777,7 +777,7 @@ __m512 test_mm512_maskz_fnmsub_ps(__mmask16 __U, __m512 __A, __m512 __B, __m512
|
|||
// CHECK: fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
|
||||
// CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}})
|
||||
// CHECK: bitcast i16 %{{.*}} to <16 x i1>
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer
|
||||
return _mm512_maskz_fnmsub_ps(__U, __A, __B, __C);
|
||||
}
|
||||
__m512d test_mm512_fmaddsub_round_pd(__m512d __A, __m512d __B, __m512d __C) {
|
||||
|
|
@ -803,7 +803,7 @@ __m512d test_mm512_maskz_fmaddsub_round_pd(__mmask8 __U, __m512d __A, __m512d __
|
|||
// CHECK-LABEL: @test_mm512_maskz_fmaddsub_round_pd
|
||||
// CHECK: @llvm.x86.avx512.vfmaddsub.pd.512
|
||||
// CHECK: bitcast i8 %{{.*}} to <8 x i1>
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer
|
||||
return _mm512_maskz_fmaddsub_round_pd(__U, __A, __B, __C, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
}
|
||||
__m512d test_mm512_fmsubadd_round_pd(__m512d __A, __m512d __B, __m512d __C) {
|
||||
|
|
@ -825,7 +825,7 @@ __m512d test_mm512_maskz_fmsubadd_round_pd(__mmask8 __U, __m512d __A, __m512d __
|
|||
// CHECK: fsub <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %{{.*}}
|
||||
// CHECK: @llvm.x86.avx512.vfmaddsub.pd.512
|
||||
// CHECK: bitcast i8 %{{.*}} to <8 x i1>
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer
|
||||
return _mm512_maskz_fmsubadd_round_pd(__U, __A, __B, __C, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
}
|
||||
__m512d test_mm512_fmaddsub_pd(__m512d __A, __m512d __B, __m512d __C) {
|
||||
|
|
@ -863,7 +863,7 @@ __m512d test_mm512_maskz_fmaddsub_pd(__mmask8 __U, __m512d __A, __m512d __B, __m
|
|||
// check: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}})
|
||||
// check: select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>, <8 x double> %{{.*}}, <8 x double> %{{.*}}
|
||||
// CHECK: bitcast i8 %{{.*}} to <8 x i1>
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer
|
||||
return _mm512_maskz_fmaddsub_pd(__U, __A, __B, __C);
|
||||
}
|
||||
__m512d test_mm512_fmsubadd_pd(__m512d __A, __m512d __B, __m512d __C) {
|
||||
|
|
@ -891,7 +891,7 @@ __m512d test_mm512_maskz_fmsubadd_pd(__mmask8 __U, __m512d __A, __m512d __B, __m
|
|||
// CHECK: call <8 x double> @llvm.fma.v8f64(<8 x double> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}})
|
||||
// CHECK: select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>, <8 x double> %{{.*}}, <8 x double> %{{.*}}
|
||||
// CHECK: bitcast i8 %{{.*}} to <8 x i1>
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
|
||||
// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> zeroinitializer
|
||||
return _mm512_maskz_fmsubadd_pd(__U, __A, __B, __C);
|
||||
}
|
||||
__m512 test_mm512_fmaddsub_round_ps(__m512 __A, __m512 __B, __m512 __C) {
|
||||
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|
@ -917,7 +917,7 @@ __m512 test_mm512_maskz_fmaddsub_round_ps(__mmask16 __U, __m512 __A, __m512 __B,
|
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// CHECK-LABEL: @test_mm512_maskz_fmaddsub_round_ps
|
||||
// CHECK: @llvm.x86.avx512.vfmaddsub.ps.512
|
||||
// CHECK: bitcast i16 %{{.*}} to <16 x i1>
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer
|
||||
return _mm512_maskz_fmaddsub_round_ps(__U, __A, __B, __C, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
}
|
||||
__m512 test_mm512_fmsubadd_round_ps(__m512 __A, __m512 __B, __m512 __C) {
|
||||
|
|
@ -939,7 +939,7 @@ __m512 test_mm512_maskz_fmsubadd_round_ps(__mmask16 __U, __m512 __A, __m512 __B,
|
|||
// CHECK: fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %{{.*}}
|
||||
// CHECK: @llvm.x86.avx512.vfmaddsub.ps.512
|
||||
// CHECK: bitcast i16 %{{.*}} to <16 x i1>
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer
|
||||
return _mm512_maskz_fmsubadd_round_ps(__U, __A, __B, __C, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
|
||||
}
|
||||
__m512 test_mm512_fmaddsub_ps(__m512 __A, __m512 __B, __m512 __C) {
|
||||
|
|
@ -977,7 +977,7 @@ __m512 test_mm512_maskz_fmaddsub_ps(__mmask16 __U, __m512 __A, __m512 __B, __m51
|
|||
// CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}})
|
||||
// CHECK: select <16 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>, <16 x float> %{{.*}}, <16 x float> %{{.*}}
|
||||
// CHECK: bitcast i16 %{{.*}} to <16 x i1>
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer
|
||||
return _mm512_maskz_fmaddsub_ps(__U, __A, __B, __C);
|
||||
}
|
||||
__m512 test_mm512_fmsubadd_ps(__m512 __A, __m512 __B, __m512 __C) {
|
||||
|
|
@ -1005,7 +1005,7 @@ __m512 test_mm512_maskz_fmsubadd_ps(__mmask16 __U, __m512 __A, __m512 __B, __m51
|
|||
// CHECK: call <16 x float> @llvm.fma.v16f32(<16 x float> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}})
|
||||
// CHECK: select <16 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>, <16 x float> %{{.*}}, <16 x float> %{{.*}}
|
||||
// CHECK: bitcast i16 %{{.*}} to <16 x i1>
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
|
||||
// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> zeroinitializer
|
||||
return _mm512_maskz_fmsubadd_ps(__U, __A, __B, __C);
|
||||
}
|
||||
__m512d test_mm512_mask3_fmsub_round_pd(__m512d __A, __m512d __B, __m512d __C, __mmask8 __U) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue