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[X86] Pass the right VT to the getZeroExtendInReg introduced in r321398 

Apparently we don't have tests for this which I didn't realize before. I'll try to fix that but wanted to fix the obvious bug.

llvm-svn: 321399
This commit is contained in:
Craig Topper 2017-12-23 06:52:03 +00:00
parent ed4a87f6a8
commit b8e7ab8231
1 changed files with 1 additions and 1 deletions
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2
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -33077,7 +33077,7 @@ static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
case ISD::ANY_EXTEND:
return Op;
case ISD::ZERO_EXTEND:
return DAG.getZeroExtendInReg(Op, DL, VT.getScalarType());
return DAG.getZeroExtendInReg(Op, DL, NarrowVT.getScalarType());
case ISD::SIGN_EXTEND:
return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
Op, DAG.getValueType(NarrowVT));