From b8d2873d93c1e40d99fae9c25505246f3815c0d7 Mon Sep 17 00:00:00 2001
From: Akira Hatanaka <ahatanaka@apple.com>
Date: Thu, 21 Jul 2016 21:39:05 +0000
Subject: [PATCH] [AArch64][Inline-Asm] Return the 32-bit floating point
 register class when constraint "w" is used on a 32-bit operand.

This enables compiling the following code, which used to error out in
the backend:

void foo1(int a) {
  asm volatile ("sqxtn h0, %s0\n" : : "w"(a):);
}

Fixes PR28633.

llvm-svn: 276344
---
 llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 2 +-
 llvm/test/CodeGen/AArch64/arm64-inline-asm.ll   | 8 ++++++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 3102e4e79cc3..bebcba7323a7 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -4703,7 +4703,7 @@ AArch64TargetLowering::getRegForInlineAsmConstraint(
         return std::make_pair(0U, &AArch64::GPR64commonRegClass);
       return std::make_pair(0U, &AArch64::GPR32commonRegClass);
     case 'w':
-      if (VT == MVT::f32)
+      if (VT.getSizeInBits() == 32)
         return std::make_pair(0U, &AArch64::FPR32RegClass);
       if (VT.getSizeInBits() == 64)
         return std::make_pair(0U, &AArch64::FPR64RegClass);
diff --git a/llvm/test/CodeGen/AArch64/arm64-inline-asm.ll b/llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
index 4d4adb10d556..f3f359380440 100644
--- a/llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
@@ -246,3 +246,11 @@ define <4 x float> @test_vreg_128bit(<4 x float> %in) nounwind {
   ; CHECK fadd v14.4s, v0.4s, v0.4s:
   ret <4 x float> %1
 }
+
+define void @test_constraint_w(i32 %a) {
+  ; CHECK: fmov [[SREG:s[0-9]+]], {{w[0-9]+}}
+  ; CHECK: sqxtn h0, [[SREG]]
+
+  tail call void asm sideeffect "sqxtn h0, ${0:s}\0A", "w"(i32 %a)
+  ret void
+}