forked from OSchip/llvm-project
[DAG] Fold neg(splat(neg(x)) -> splat(x)
This add as a fold of sub(0, splat(sub(0, x))) -> splat(x). This can come up in the lowering of right shifts under AArch64, where we generate a shift left of a negated number. Differential Revision: https://reviews.llvm.org/D103755
This commit is contained in:
David Green
parent
0f3bc00a7d
commit
b8c8bb0769
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@ -3308,6 +3308,17 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
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!TLI.isOperationLegalOrCustom(ISD::ABS, VT) &&
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TLI.expandABS(N1.getNode(), Result, DAG, true))
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return Result;
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// Fold neg(splat(neg(x)) -> splat(x)
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if (VT.isVector()) {
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SDValue N1S = DAG.getSplatValue(N1, true);
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if (N1S && N1S.getOpcode() == ISD::SUB &&
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isNullConstant(N1S.getOperand(0))) {
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if (VT.isScalableVector())
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return DAG.getSplatVector(VT, DL, N1S.getOperand(1));
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return DAG.getSplatBuildVector(VT, DL, N1S.getOperand(1));
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}
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}
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}
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// Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
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@ -4,9 +4,7 @@
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define <2 x i64> @shr64x2(<2 x i64> %a, i64 %b) {
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; CHECK-LABEL: shr64x2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg x8, x0
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; CHECK-NEXT: dup v1.2d, x8
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; CHECK-NEXT: neg v1.2d, v1.2d
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; CHECK-NEXT: dup v1.2d, x0
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; CHECK-NEXT: sshl v0.2d, v0.2d, v1.2d
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; CHECK-NEXT: ret
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entry:
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@ -20,9 +18,7 @@ entry:
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define <4 x i32> @shr32x4(<4 x i32> %a, i32 %b) {
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; CHECK-LABEL: shr32x4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.4s, w8
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; CHECK-NEXT: neg v1.4s, v1.4s
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; CHECK-NEXT: dup v1.4s, w0
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; CHECK-NEXT: sshl v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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entry:
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@ -36,9 +32,7 @@ entry:
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define <4 x i32> @shr32x4undef(<4 x i32> %a, i32 %b) {
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; CHECK-LABEL: shr32x4undef:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.4s, w8
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; CHECK-NEXT: neg v1.4s, v1.4s
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; CHECK-NEXT: dup v1.4s, w0
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; CHECK-NEXT: sshl v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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entry:
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@ -52,9 +46,7 @@ entry:
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define <8 x i16> @shr16x8(<8 x i16> %a, i16 %b) {
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; CHECK-LABEL: shr16x8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.8h, w8
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; CHECK-NEXT: neg v1.8h, v1.8h
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; CHECK-NEXT: dup v1.8h, w0
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; CHECK-NEXT: sshl v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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entry:
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@ -68,9 +60,7 @@ entry:
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define <16 x i8> @shr8x16(<16 x i8> %a, i8 %b) {
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; CHECK-LABEL: shr8x16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.16b, w8
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; CHECK-NEXT: neg v1.16b, v1.16b
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; CHECK-NEXT: dup v1.16b, w0
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; CHECK-NEXT: sshl v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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entry:
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@ -84,9 +74,7 @@ entry:
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define <1 x i64> @shr64x1(<1 x i64> %a, i64 %b) {
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; CHECK-LABEL: shr64x1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg x8, x0
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: neg d1, d1
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; CHECK-NEXT: fmov d1, x0
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; CHECK-NEXT: sshl d0, d0, d1
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; CHECK-NEXT: ret
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entry:
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@ -99,9 +87,7 @@ entry:
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define <2 x i32> @shr32x2(<2 x i32> %a, i32 %b) {
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; CHECK-LABEL: shr32x2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.2s, w8
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; CHECK-NEXT: neg v1.2s, v1.2s
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; CHECK-NEXT: dup v1.2s, w0
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; CHECK-NEXT: sshl v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ret
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entry:
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@ -115,9 +101,7 @@ entry:
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define <4 x i16> @shr16x4(<4 x i16> %a, i16 %b) {
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; CHECK-LABEL: shr16x4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.4h, w8
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; CHECK-NEXT: neg v1.4h, v1.4h
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; CHECK-NEXT: dup v1.4h, w0
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; CHECK-NEXT: sshl v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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entry:
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@ -131,9 +115,7 @@ entry:
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define <8 x i8> @shr8x8(<8 x i8> %a, i8 %b) {
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; CHECK-LABEL: shr8x8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.8b, w8
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; CHECK-NEXT: neg v1.8b, v1.8b
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; CHECK-NEXT: dup v1.8b, w0
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; CHECK-NEXT: sshl v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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entry:
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@ -147,9 +129,7 @@ entry:
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define <2 x i64> @lshr64x2(<2 x i64> %a, i64 %b) {
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; CHECK-LABEL: lshr64x2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg x8, x0
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; CHECK-NEXT: dup v1.2d, x8
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; CHECK-NEXT: neg v1.2d, v1.2d
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; CHECK-NEXT: dup v1.2d, x0
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; CHECK-NEXT: ushl v0.2d, v0.2d, v1.2d
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; CHECK-NEXT: ret
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entry:
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@ -163,9 +143,7 @@ entry:
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define <4 x i32> @lshr32x4(<4 x i32> %a, i32 %b) {
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; CHECK-LABEL: lshr32x4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.4s, w8
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; CHECK-NEXT: neg v1.4s, v1.4s
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; CHECK-NEXT: dup v1.4s, w0
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; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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entry:
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@ -179,9 +157,7 @@ entry:
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define <4 x i32> @lshr32x4undef(<4 x i32> %a, i32 %b) {
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; CHECK-LABEL: lshr32x4undef:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.4s, w8
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; CHECK-NEXT: neg v1.4s, v1.4s
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; CHECK-NEXT: dup v1.4s, w0
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; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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entry:
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@ -195,9 +171,7 @@ entry:
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define <8 x i16> @lshr16x8(<8 x i16> %a, i16 %b) {
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; CHECK-LABEL: lshr16x8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.8h, w8
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; CHECK-NEXT: neg v1.8h, v1.8h
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; CHECK-NEXT: dup v1.8h, w0
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; CHECK-NEXT: ushl v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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entry:
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@ -211,9 +185,7 @@ entry:
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define <16 x i8> @lshr8x16(<16 x i8> %a, i8 %b) {
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; CHECK-LABEL: lshr8x16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.16b, w8
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; CHECK-NEXT: neg v1.16b, v1.16b
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; CHECK-NEXT: dup v1.16b, w0
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; CHECK-NEXT: ushl v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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entry:
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@ -227,9 +199,7 @@ entry:
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define <1 x i64> @lshr64x1(<1 x i64> %a, i64 %b) {
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; CHECK-LABEL: lshr64x1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg x8, x0
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: neg d1, d1
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; CHECK-NEXT: fmov d1, x0
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; CHECK-NEXT: ushl d0, d0, d1
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; CHECK-NEXT: ret
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entry:
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@ -242,9 +212,7 @@ entry:
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define <2 x i32> @lshr32x2(<2 x i32> %a, i32 %b) {
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; CHECK-LABEL: lshr32x2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.2s, w8
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; CHECK-NEXT: neg v1.2s, v1.2s
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; CHECK-NEXT: dup v1.2s, w0
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; CHECK-NEXT: ushl v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ret
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entry:
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@ -258,9 +226,7 @@ entry:
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define <4 x i16> @lshr16x4(<4 x i16> %a, i16 %b) {
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; CHECK-LABEL: lshr16x4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.4h, w8
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; CHECK-NEXT: neg v1.4h, v1.4h
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; CHECK-NEXT: dup v1.4h, w0
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; CHECK-NEXT: ushl v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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entry:
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@ -274,9 +240,7 @@ entry:
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define <8 x i8> @lshr8x8(<8 x i8> %a, i8 %b) {
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; CHECK-LABEL: lshr8x8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v1.8b, w8
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; CHECK-NEXT: neg v1.8b, v1.8b
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; CHECK-NEXT: dup v1.8b, w0
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; CHECK-NEXT: ushl v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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entry:
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@ -603,9 +567,7 @@ entry:
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define <vscale x 16 x i8> @subsub(<vscale x 16 x i8> %a, i8 %b) {
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; CHECK-LABEL: subsub:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: mov z0.b, w8
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; CHECK-NEXT: subr z0.b, z0.b, #0 // =0x0
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; CHECK-NEXT: mov z0.b, w0
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; CHECK-NEXT: ret
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entry:
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%sub = sub i8 0, %b
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@ -4,9 +4,7 @@
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define <16 x i8> @subsubii8(<16 x i8> %a, i8 %b) {
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; CHECK-LABEL: subsubii8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: dup v0.16b, w8
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; CHECK-NEXT: neg v0.16b, v0.16b
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; CHECK-NEXT: dup v0.16b, w0
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; CHECK-NEXT: ret
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entry:
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%sub = sub i8 0, %b
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@ -19,9 +17,7 @@ entry:
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define <vscale x 16 x i8> @subsubni8(<vscale x 16 x i8> %a, i8 %b) {
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; CHECK-LABEL: subsubni8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: neg w8, w0
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; CHECK-NEXT: mov z0.b, w8
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; CHECK-NEXT: subr z0.b, z0.b, #0 // =0x0
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; CHECK-NEXT: mov z0.b, w0
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; CHECK-NEXT: ret
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entry:
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%sub = sub i8 0, %b
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