forked from OSchip/llvm-project
[GlobalISel][AArch64] Use a GISelPredicateCode to select llvm.aarch64.stlxr.*
Remove manual selection code for this intrinsic and use a GISelPredicateCode instead. This allows us to fully select this intrinsic without any tricky custom C++ matching. Differential Revision: https://reviews.llvm.org/D65780 llvm-svn: 370380
This commit is contained in:
Jessica Paquette
parent
907452107d
commit
b8b23a1648
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@ -333,22 +333,30 @@ def : Pat<(stxr_4 (and GPR64:$val, 0xffffffff), GPR64sp:$addr),
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def stlxr_1 : PatFrag<(ops node:$val, node:$ptr),
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(int_aarch64_stlxr node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
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}]>;
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}]> {
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let GISelPredicateCode = [{ return isLoadStoreOfNumBytes(MI, 1); }];
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}
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def stlxr_2 : PatFrag<(ops node:$val, node:$ptr),
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(int_aarch64_stlxr node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
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}]>;
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}]> {
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let GISelPredicateCode = [{ return isLoadStoreOfNumBytes(MI, 2); }];
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}
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def stlxr_4 : PatFrag<(ops node:$val, node:$ptr),
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(int_aarch64_stlxr node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
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}]>;
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}]> {
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let GISelPredicateCode = [{ return isLoadStoreOfNumBytes(MI, 4); }];
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}
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def stlxr_8 : PatFrag<(ops node:$val, node:$ptr),
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(int_aarch64_stlxr node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
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}]>;
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}]> {
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let GISelPredicateCode = [{ return isLoadStoreOfNumBytes(MI, 8); }];
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}
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def : Pat<(stlxr_1 GPR64:$val, GPR64sp:$addr),
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@ -438,4 +446,3 @@ let Predicates = [HasLSE] in {
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defm : LDOPregister_patterns_mod<"LDADD", "atomic_load_sub", "SUB">;
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defm : LDOPregister_patterns_mod<"LDCLR", "atomic_load_and", "ORN">;
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}
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@ -3912,23 +3912,6 @@ static unsigned findIntrinsicID(MachineInstr &I) {
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return IntrinOp->getIntrinsicID();
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}
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/// Helper function to emit the correct opcode for a llvm.aarch64.stlxr
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/// intrinsic.
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static unsigned getStlxrOpcode(unsigned NumBytesToStore) {
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switch (NumBytesToStore) {
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// TODO: 1 and 2 byte stores
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case 4:
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return AArch64::STLXRW;
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case 8:
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return AArch64::STLXRX;
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default:
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LLVM_DEBUG(dbgs() << "Unexpected number of bytes to store! ("
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<< NumBytesToStore << ")\n");
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break;
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}
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return 0;
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}
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bool AArch64InstructionSelector::selectIntrinsicWithSideEffects(
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MachineInstr &I, MachineRegisterInfo &MRI) const {
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// Find the intrinsic ID.
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@ -3949,48 +3932,6 @@ bool AArch64InstructionSelector::selectIntrinsicWithSideEffects(
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return false;
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MIRBuilder.buildInstr(AArch64::BRK, {}, {}).addImm(0xF000);
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break;
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case Intrinsic::aarch64_stlxr:
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Register StatReg = I.getOperand(0).getReg();
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assert(RBI.getSizeInBits(StatReg, MRI, TRI) == 32 &&
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"Status register must be 32 bits!");
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Register SrcReg = I.getOperand(2).getReg();
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if (RBI.getSizeInBits(SrcReg, MRI, TRI) != 64) {
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LLVM_DEBUG(dbgs() << "Only support 64-bit sources right now.\n");
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return false;
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}
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Register PtrReg = I.getOperand(3).getReg();
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assert(MRI.getType(PtrReg).isPointer() && "Expected pointer operand");
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// Expect only one memory operand.
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if (!I.hasOneMemOperand())
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return false;
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const MachineMemOperand *MemOp = *I.memoperands_begin();
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unsigned NumBytesToStore = MemOp->getSize();
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unsigned Opc = getStlxrOpcode(NumBytesToStore);
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if (!Opc)
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return false;
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unsigned NumBitsToStore = NumBytesToStore * 8;
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if (NumBitsToStore != 64) {
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// The intrinsic always has a 64-bit source, but we might actually want
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// a differently-sized source for the instruction. Try to get it.
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// TODO: For 1 and 2-byte stores, this will have a G_AND. For now, let's
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// just handle 4-byte stores.
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// TODO: If we don't find a G_ZEXT, we'll have to truncate the value down
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// to the right size for the STLXR.
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MachineInstr *Zext = getOpcodeDef(TargetOpcode::G_ZEXT, SrcReg, MRI);
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if (!Zext)
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return false;
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SrcReg = Zext->getOperand(1).getReg();
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// We should get an appropriately-sized register here.
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if (RBI.getSizeInBits(SrcReg, MRI, TRI) != NumBitsToStore)
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return false;
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}
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auto StoreMI = MIRBuilder.buildInstr(Opc, {StatReg}, {SrcReg, PtrReg})
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.addMemOperand(*I.memoperands_begin());
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constrainSelectedInstRegOperands(*StoreMI, TII, TRI, RBI);
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}
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I.eraseFromParent();
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@ -9,6 +9,9 @@
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define i32 @test_store_release_i32(i32 %a, i64* %addr) {
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ret i32 %a
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}
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define void @test_store_release_i8(i32, i8 %val, i8* %addr) { ret void }
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define void @test_store_release_i16(i32, i16 %val, i16* %addr) { ret void }
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...
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---
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name: test_store_release_i64
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@ -58,3 +61,61 @@ body: |
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RET_ReallyLR implicit $w0
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...
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---
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name: test_store_release_i8
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1, $x2
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; CHECK-LABEL: name: test_store_release_i8
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; CHECK: liveins: $w0, $w1, $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
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; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64all = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
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; CHECK: early-clobber %5:gpr32 = STLXRB [[COPY2]], [[COPY1]] :: (volatile store 1 into %ir.addr)
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; CHECK: $w0 = COPY %5
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; CHECK: RET_ReallyLR implicit $w0
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%3:gpr(s32) = COPY $w1
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%2:gpr(p0) = COPY $x2
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%6:gpr(s64) = G_CONSTANT i64 255
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%7:gpr(s64) = G_ANYEXT %3(s32)
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%4:gpr(s64) = G_AND %7, %6
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%5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %4(s64), %2(p0) :: (volatile store 1 into %ir.addr)
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: test_store_release_i16
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1, $x2
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; CHECK-LABEL: name: test_store_release_i16
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; CHECK: liveins: $w0, $w1, $x2
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x2
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; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64all = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[INSERT_SUBREG]].sub_32
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; CHECK: early-clobber %5:gpr32 = STLXRH [[COPY2]], [[COPY1]] :: (volatile store 2 into %ir.addr)
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; CHECK: $w0 = COPY %5
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; CHECK: RET_ReallyLR implicit $w0
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%3:gpr(s32) = COPY $w1
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%2:gpr(p0) = COPY $x2
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%6:gpr(s64) = G_CONSTANT i64 65535
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%7:gpr(s64) = G_ANYEXT %3(s32)
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%4:gpr(s64) = G_AND %7, %6
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%5:gpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.stlxr), %4(s64), %2(p0) :: (volatile store 2 into %ir.addr)
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$w0 = COPY %5(s32)
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RET_ReallyLR implicit $w0
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@ -268,21 +268,31 @@ declare i64 @llvm.aarch64.ldaxr.p0i16(i16*) nounwind
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declare i64 @llvm.aarch64.ldaxr.p0i32(i32*) nounwind
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declare i64 @llvm.aarch64.ldaxr.p0i64(i64*) nounwind
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; FALLBACK-NOT: remark:{{.*}}test_store_release_i8
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define i32 @test_store_release_i8(i32, i8 %val, i8* %addr) {
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; CHECK-LABEL: test_store_release_i8:
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; CHECK-NOT: uxtb
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; CHECK-NOT: and
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; CHECK: stlxrb w0, w1, [x2]
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; GISEL-LABEL: test_store_release_i8:
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; GISEL-NOT: uxtb
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; GISEL-NOT: and
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; GISEL: stlxrb w0, w1, [x2]
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%extval = zext i8 %val to i64
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%res = call i32 @llvm.aarch64.stlxr.p0i8(i64 %extval, i8* %addr)
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ret i32 %res
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}
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; FALLBACK-NOT: remark:{{.*}}test_store_release_i16
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define i32 @test_store_release_i16(i32, i16 %val, i16* %addr) {
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; CHECK-LABEL: test_store_release_i16:
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; CHECK-NOT: uxth
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; CHECK-NOT: and
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; CHECK: stlxrh w0, w1, [x2]
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; GISEL-LABEL: test_store_release_i16:
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; GISEL-NOT: uxth
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; GISEL-NOT: and
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; GISEL: stlxrh w0, w1, [x2]
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%extval = zext i16 %val to i64
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%res = call i32 @llvm.aarch64.stlxr.p0i16(i64 %extval, i16* %addr)
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ret i32 %res
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