forked from OSchip/llvm-project
fix a bunch of partially ambiguous patterns on ARM. As an
example, this: (set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin)) is ambiguous because DPR contains both f64 and v2f32. tblgen currently accidentally picks f64 because it's first in the regclass. llvm-svn: 97955
This commit is contained in:
Chris Lattner
parent
8a16769b61
commit
b8a7427636
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@ -21,7 +21,7 @@ def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
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def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
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def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
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def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
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def SDT_ARMCMov : SDTypeProfile<1, 3,
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[SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
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@ -2707,21 +2707,21 @@ def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$dst),
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}
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def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
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(v16i8 (INSERT_SUBREG QPR:$src1,
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(VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
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(v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
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(DSubReg_i8_reg imm:$lane))),
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GPR:$src2, (SubReg_i8_lane imm:$lane)),
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GPR:$src2, (SubReg_i8_lane imm:$lane))),
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(DSubReg_i8_reg imm:$lane)))>;
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def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
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(v8i16 (INSERT_SUBREG QPR:$src1,
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(VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
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(v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
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(DSubReg_i16_reg imm:$lane))),
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GPR:$src2, (SubReg_i16_lane imm:$lane)),
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GPR:$src2, (SubReg_i16_lane imm:$lane))),
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(DSubReg_i16_reg imm:$lane)))>;
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def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
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(v4i32 (INSERT_SUBREG QPR:$src1,
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(VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
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(v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
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(DSubReg_i32_reg imm:$lane))),
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GPR:$src2, (SubReg_i32_lane imm:$lane)),
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GPR:$src2, (SubReg_i32_lane imm:$lane))),
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(DSubReg_i32_reg imm:$lane)))>;
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def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
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@ -3093,16 +3093,17 @@ def VTBX4
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class N2VSPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
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: NEONFPPat<(ResTy (OpNode SPR:$a)),
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(EXTRACT_SUBREG (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
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SPR:$a, arm_ssubreg_0)),
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(EXTRACT_SUBREG (OpTy (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)),
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SPR:$a, arm_ssubreg_0))),
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arm_ssubreg_0)>;
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class N3VSPat<SDNode OpNode, NeonI Inst>
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: NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
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(EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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SPR:$a, arm_ssubreg_0),
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(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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SPR:$b, arm_ssubreg_0)),
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(EXTRACT_SUBREG (v2f32
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(Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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SPR:$a, arm_ssubreg_0),
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(INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
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SPR:$b, arm_ssubreg_0))),
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arm_ssubreg_0)>;
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class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
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@ -57,7 +57,7 @@ def vfp_f64imm : Operand<f64>,
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let canFoldAsLoad = 1, isReMaterializable = 1 in {
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def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr),
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IIC_fpLoad64, "vldr", ".64\t$dst, $addr",
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[(set DPR:$dst, (load addrmode5:$addr))]>;
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[(set DPR:$dst, (f64 (load addrmode5:$addr)))]>;
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def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
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IIC_fpLoad32, "vldr", ".32\t$dst, $addr",
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@ -66,7 +66,7 @@ def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$dst), (ins addrmode5:$addr),
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def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$src, addrmode5:$addr),
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IIC_fpStore64, "vstr", ".64\t$src, $addr",
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[(store DPR:$src, addrmode5:$addr)]>;
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[(store (f64 DPR:$src), addrmode5:$addr)]>;
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def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
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IIC_fpStore32, "vstr", ".32\t$src, $addr",
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@ -116,7 +116,7 @@ def VSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
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def VADDD : ADbI<0b11100, 0b11, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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IIC_fpALU64, "vadd", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fadd DPR:$a, DPR:$b))]>;
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[(set DPR:$dst, (fadd DPR:$a, (f64 DPR:$b)))]>;
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def VADDS : ASbIn<0b11100, 0b11, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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IIC_fpALU32, "vadd", ".f32\t$dst, $a, $b",
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@ -126,7 +126,7 @@ def VADDS : ASbIn<0b11100, 0b11, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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let Defs = [FPSCR] in {
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def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0, (outs), (ins DPR:$a, DPR:$b),
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IIC_fpCMP64, "vcmpe", ".f64\t$a, $b",
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[(arm_cmpfp DPR:$a, DPR:$b)]>;
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[(arm_cmpfp DPR:$a, (f64 DPR:$b))]>;
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def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins DPR:$a, DPR:$b),
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IIC_fpCMP64, "vcmp", ".f64\t$a, $b",
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@ -143,7 +143,7 @@ def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins SPR:$a, SPR:$b),
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def VDIVD : ADbI<0b11101, 0b00, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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IIC_fpDIV64, "vdiv", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fdiv DPR:$a, DPR:$b))]>;
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[(set DPR:$dst, (fdiv DPR:$a, (f64 DPR:$b)))]>;
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def VDIVS : ASbI<0b11101, 0b00, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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IIC_fpDIV32, "vdiv", ".f32\t$dst, $a, $b",
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@ -151,7 +151,7 @@ def VDIVS : ASbI<0b11101, 0b00, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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def VMULD : ADbI<0b11100, 0b10, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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IIC_fpMUL64, "vmul", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fmul DPR:$a, DPR:$b))]>;
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[(set DPR:$dst, (fmul DPR:$a, (f64 DPR:$b)))]>;
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def VMULS : ASbIn<0b11100, 0b10, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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IIC_fpMUL32, "vmul", ".f32\t$dst, $a, $b",
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@ -159,14 +159,14 @@ def VMULS : ASbIn<0b11100, 0b10, 0, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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def VNMULD : ADbI<0b11100, 0b10, 1, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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IIC_fpMUL64, "vnmul", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fneg (fmul DPR:$a, DPR:$b)))]>;
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[(set DPR:$dst, (fneg (fmul DPR:$a, (f64 DPR:$b))))]>;
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def VNMULS : ASbI<0b11100, 0b10, 1, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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IIC_fpMUL32, "vnmul", ".f32\t$dst, $a, $b",
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[(set SPR:$dst, (fneg (fmul SPR:$a, SPR:$b)))]>;
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// Match reassociated forms only if not sign dependent rounding.
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def : Pat<(fmul (fneg DPR:$a), DPR:$b),
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def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
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(VNMULD DPR:$a, DPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
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def : Pat<(fmul (fneg SPR:$a), SPR:$b),
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(VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
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@ -174,7 +174,7 @@ def : Pat<(fmul (fneg SPR:$a), SPR:$b),
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def VSUBD : ADbI<0b11100, 0b11, 1, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
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IIC_fpALU64, "vsub", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fsub DPR:$a, DPR:$b))]>;
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[(set DPR:$dst, (fsub DPR:$a, (f64 DPR:$b)))]>;
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def VSUBS : ASbIn<0b11100, 0b11, 1, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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IIC_fpALU32, "vsub", ".f32\t$dst, $a, $b",
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@ -186,7 +186,7 @@ def VSUBS : ASbIn<0b11100, 0b11, 1, 0, (outs SPR:$dst), (ins SPR:$a, SPR:$b),
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def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0, (outs DPR:$dst), (ins DPR:$a),
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IIC_fpUNA64, "vabs", ".f64\t$dst, $a",
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[(set DPR:$dst, (fabs DPR:$a))]>;
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[(set DPR:$dst, (fabs (f64 DPR:$a)))]>;
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def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,(outs SPR:$dst), (ins SPR:$a),
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IIC_fpUNA32, "vabs", ".f32\t$dst, $a",
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@ -195,7 +195,7 @@ def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,(outs SPR:$dst), (ins SPR:$a),
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let Defs = [FPSCR] in {
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def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0, (outs), (ins DPR:$a),
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IIC_fpCMP64, "vcmpe", ".f64\t$a, #0",
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[(arm_cmpfp0 DPR:$a)]>;
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[(arm_cmpfp0 (f64 DPR:$a))]>;
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def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, (outs), (ins DPR:$a),
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IIC_fpCMP64, "vcmp", ".f64\t$a, #0",
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@ -253,7 +253,7 @@ def VMOVS: ASuI<0b11101, 0b11, 0b0000, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
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def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, (outs DPR:$dst), (ins DPR:$a),
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IIC_fpUNA64, "vneg", ".f64\t$dst, $a",
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[(set DPR:$dst, (fneg DPR:$a))]>;
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[(set DPR:$dst, (fneg (f64 DPR:$a)))]>;
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def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,(outs SPR:$dst), (ins SPR:$a),
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IIC_fpUNA32, "vneg", ".f32\t$dst, $a",
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@ -261,7 +261,7 @@ def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,(outs SPR:$dst), (ins SPR:$a),
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def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0, (outs DPR:$dst), (ins DPR:$a),
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IIC_fpSQRT64, "vsqrt", ".f64\t$dst, $a",
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[(set DPR:$dst, (fsqrt DPR:$a))]>;
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[(set DPR:$dst, (fsqrt (f64 DPR:$a)))]>;
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def VSQRTS : ASuI<0b11101, 0b11, 0b0001, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
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IIC_fpSQRT32, "vsqrt", ".f32\t$dst, $a",
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@ -325,7 +325,7 @@ def VMOVSRR : AVConv5I<0b11000100, 0b1010,
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def VSITOD : AVConv1I<0b11101, 0b11, 0b1000, 0b1011,
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(outs DPR:$dst), (ins SPR:$a),
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IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a",
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[(set DPR:$dst, (arm_sitof SPR:$a))]> {
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[(set DPR:$dst, (f64 (arm_sitof SPR:$a)))]> {
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let Inst{7} = 1; // s32
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}
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@ -339,7 +339,7 @@ def VSITOS : AVConv1In<0b11101, 0b11, 0b1000, 0b1010,
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def VUITOD : AVConv1I<0b11101, 0b11, 0b1000, 0b1011,
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(outs DPR:$dst), (ins SPR:$a),
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IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a",
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[(set DPR:$dst, (arm_uitof SPR:$a))]> {
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[(set DPR:$dst, (f64 (arm_uitof SPR:$a)))]> {
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let Inst{7} = 0; // u32
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}
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@ -356,7 +356,7 @@ def VUITOS : AVConv1In<0b11101, 0b11, 0b1000, 0b1010,
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def VTOSIZD : AVConv1I<0b11101, 0b11, 0b1101, 0b1011,
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(outs SPR:$dst), (ins DPR:$a),
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IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a",
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[(set SPR:$dst, (arm_ftosi DPR:$a))]> {
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[(set SPR:$dst, (arm_ftosi (f64 DPR:$a)))]> {
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let Inst{7} = 1; // Z bit
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}
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@ -370,7 +370,7 @@ def VTOSIZS : AVConv1In<0b11101, 0b11, 0b1101, 0b1010,
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def VTOUIZD : AVConv1I<0b11101, 0b11, 0b1100, 0b1011,
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(outs SPR:$dst), (ins DPR:$a),
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IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a",
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[(set SPR:$dst, (arm_ftoui DPR:$a))]> {
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[(set SPR:$dst, (arm_ftoui (f64 DPR:$a)))]> {
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let Inst{7} = 1; // Z bit
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}
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@ -514,7 +514,8 @@ def VULTOD : AVConv1XI<0b11101, 0b11, 0b1011, 0b1011, 1,
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def VMLAD : ADbI<0b11100, 0b00, 0, 0,
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(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
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IIC_fpMAC64, "vmla", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
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[(set DPR:$dst, (fadd (fmul DPR:$a, DPR:$b),
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(f64 DPR:$dstin)))]>,
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RegConstraint<"$dstin = $dst">;
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def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
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@ -526,7 +527,8 @@ def VMLAS : ASbIn<0b11100, 0b00, 0, 0,
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def VNMLSD : ADbI<0b11100, 0b01, 0, 0,
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(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
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IIC_fpMAC64, "vnmls", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b), DPR:$dstin))]>,
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[(set DPR:$dst, (fsub (fmul DPR:$a, DPR:$b),
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(f64 DPR:$dstin)))]>,
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RegConstraint<"$dstin = $dst">;
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def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
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@ -538,7 +540,8 @@ def VNMLSS : ASbI<0b11100, 0b01, 0, 0,
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def VMLSD : ADbI<0b11100, 0b00, 1, 0,
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(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
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IIC_fpMAC64, "vmls", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
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[(set DPR:$dst, (fadd (fneg (fmul DPR:$a, DPR:$b)),
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(f64 DPR:$dstin)))]>,
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RegConstraint<"$dstin = $dst">;
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def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
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@ -547,7 +550,7 @@ def VMLSS : ASbIn<0b11100, 0b00, 1, 0,
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[(set SPR:$dst, (fadd (fneg (fmul SPR:$a, SPR:$b)), SPR:$dstin))]>,
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RegConstraint<"$dstin = $dst">;
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def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, DPR:$b)),
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def : Pat<(fsub DPR:$dstin, (fmul DPR:$a, (f64 DPR:$b))),
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(VMLSD DPR:$dstin, DPR:$a, DPR:$b)>, Requires<[DontUseNEONForFP]>;
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def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
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(VMLSS SPR:$dstin, SPR:$a, SPR:$b)>, Requires<[DontUseNEONForFP]>;
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@ -555,7 +558,8 @@ def : Pat<(fsub SPR:$dstin, (fmul SPR:$a, SPR:$b)),
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def VNMLAD : ADbI<0b11100, 0b01, 1, 0,
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(outs DPR:$dst), (ins DPR:$dstin, DPR:$a, DPR:$b),
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IIC_fpMAC64, "vnmla", ".f64\t$dst, $a, $b",
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[(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))]>,
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[(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)),
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(f64 DPR:$dstin)))]>,
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RegConstraint<"$dstin = $dst">;
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def VNMLAS : ASbI<0b11100, 0b01, 1, 0,
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