forked from OSchip/llvm-project
[UpdateTestChecks] Remove bug-exposing test
Remove RISCV codegen tests for --include-generated-funcs because apparently MachineOutliner has a bug on that target that is exposed by expensive-checks.
This commit is contained in:
David Greene
parent
b522f09d96
commit
b877933784
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@ -1,63 +0,0 @@
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; RUN: llc -enable-machine-outliner -mtriple=riscv32-unknown-linux < %s | FileCheck %s
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@x = global i32 0, align 4
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define i32 @check_boundaries() #0 {
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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%3 = alloca i32, align 4
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%4 = alloca i32, align 4
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%5 = alloca i32, align 4
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store i32 0, i32* %1, align 4
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store i32 0, i32* %2, align 4
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%6 = load i32, i32* %2, align 4
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%7 = icmp ne i32 %6, 0
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br i1 %7, label %9, label %8
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store i32 1, i32* %2, align 4
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store i32 2, i32* %3, align 4
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store i32 3, i32* %4, align 4
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store i32 4, i32* %5, align 4
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br label %10
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store i32 1, i32* %4, align 4
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br label %10
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%11 = load i32, i32* %2, align 4
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%12 = icmp ne i32 %11, 0
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br i1 %12, label %14, label %13
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store i32 1, i32* %2, align 4
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store i32 2, i32* %3, align 4
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store i32 3, i32* %4, align 4
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store i32 4, i32* %5, align 4
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br label %15
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store i32 1, i32* %4, align 4
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br label %15
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ret i32 0
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}
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define i32 @main() #0 {
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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%3 = alloca i32, align 4
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%4 = alloca i32, align 4
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%5 = alloca i32, align 4
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store i32 0, i32* %1, align 4
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store i32 0, i32* @x, align 4
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store i32 1, i32* %2, align 4
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store i32 2, i32* %3, align 4
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store i32 3, i32* %4, align 4
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store i32 4, i32* %5, align 4
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store i32 1, i32* @x, align 4
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call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
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store i32 1, i32* %2, align 4
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store i32 2, i32* %3, align 4
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store i32 3, i32* %4, align 4
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store i32 4, i32* %5, align 4
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ret i32 0
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}
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attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
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@ -1,143 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --include-generated-funcs
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; RUN: llc -enable-machine-outliner -mtriple=riscv32-unknown-linux < %s | FileCheck %s
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@x = global i32 0, align 4
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define i32 @check_boundaries() #0 {
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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%3 = alloca i32, align 4
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%4 = alloca i32, align 4
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%5 = alloca i32, align 4
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store i32 0, i32* %1, align 4
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store i32 0, i32* %2, align 4
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%6 = load i32, i32* %2, align 4
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%7 = icmp ne i32 %6, 0
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br i1 %7, label %9, label %8
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store i32 1, i32* %2, align 4
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store i32 2, i32* %3, align 4
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store i32 3, i32* %4, align 4
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store i32 4, i32* %5, align 4
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br label %10
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store i32 1, i32* %4, align 4
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br label %10
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%11 = load i32, i32* %2, align 4
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%12 = icmp ne i32 %11, 0
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br i1 %12, label %14, label %13
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store i32 1, i32* %2, align 4
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store i32 2, i32* %3, align 4
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store i32 3, i32* %4, align 4
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store i32 4, i32* %5, align 4
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br label %15
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store i32 1, i32* %4, align 4
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br label %15
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ret i32 0
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}
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define i32 @main() #0 {
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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%3 = alloca i32, align 4
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%4 = alloca i32, align 4
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%5 = alloca i32, align 4
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store i32 0, i32* %1, align 4
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store i32 0, i32* @x, align 4
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store i32 1, i32* %2, align 4
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store i32 2, i32* %3, align 4
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store i32 3, i32* %4, align 4
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store i32 4, i32* %5, align 4
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store i32 1, i32* @x, align 4
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call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
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store i32 1, i32* %2, align 4
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store i32 2, i32* %3, align 4
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store i32 3, i32* %4, align 4
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store i32 4, i32* %5, align 4
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ret i32 0
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}
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attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
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; CHECK-LABEL: check_boundaries:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -32
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: sw ra, 28(sp)
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; CHECK-NEXT: sw s0, 24(sp)
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; CHECK-NEXT: .cfi_offset ra, -4
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; CHECK-NEXT: .cfi_offset s0, -8
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; CHECK-NEXT: addi s0, sp, 32
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; CHECK-NEXT: .cfi_def_cfa s0, 0
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; CHECK-NEXT: sw zero, -12(s0)
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; CHECK-NEXT: sw zero, -16(s0)
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; CHECK-NEXT: addi a0, zero, 1
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; CHECK-NEXT: beqz zero, .LBB0_3
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: sw a0, -24(s0)
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; CHECK-NEXT: lw a0, -16(s0)
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; CHECK-NEXT: beqz a0, .LBB0_4
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: addi a0, zero, 1
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; CHECK-NEXT: sw a0, -24(s0)
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; CHECK-NEXT: j .LBB0_5
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; CHECK-NEXT: .LBB0_3:
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; CHECK-NEXT: call t0, OUTLINED_FUNCTION_0
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; CHECK-NEXT: lw a0, -16(s0)
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; CHECK-NEXT: bnez a0, .LBB0_2
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; CHECK-NEXT: .LBB0_4:
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; CHECK-NEXT: addi a0, zero, 1
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; CHECK-NEXT: call t0, OUTLINED_FUNCTION_0
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; CHECK-NEXT: .LBB0_5:
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; CHECK-NEXT: mv a0, zero
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; CHECK-NEXT: lw s0, 24(sp)
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; CHECK-NEXT: lw ra, 28(sp)
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; CHECK-NEXT: addi sp, sp, 32
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; CHECK-NEXT: ret
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;
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; CHECK-LABEL: main:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -32
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: sw ra, 28(sp)
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; CHECK-NEXT: sw s0, 24(sp)
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; CHECK-NEXT: .cfi_offset ra, -4
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; CHECK-NEXT: .cfi_offset s0, -8
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; CHECK-NEXT: addi s0, sp, 32
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; CHECK-NEXT: .cfi_def_cfa s0, 0
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; CHECK-NEXT: sw zero, -12(s0)
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; CHECK-NEXT: lui a0, %hi(x)
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; CHECK-NEXT: addi a1, zero, 1
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; CHECK-NEXT: sw a1, -16(s0)
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; CHECK-NEXT: addi a2, zero, 2
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; CHECK-NEXT: sw a2, -20(s0)
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; CHECK-NEXT: addi a3, zero, 3
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; CHECK-NEXT: sw a3, -24(s0)
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; CHECK-NEXT: addi a4, zero, 4
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; CHECK-NEXT: sw a4, -28(s0)
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; CHECK-NEXT: sw a1, %lo(x)(a0)
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; CHECK-NEXT: #APP
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: sw a1, -16(s0)
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; CHECK-NEXT: sw a2, -20(s0)
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; CHECK-NEXT: sw a3, -24(s0)
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; CHECK-NEXT: sw a4, -28(s0)
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; CHECK-NEXT: mv a0, zero
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; CHECK-NEXT: lw s0, 24(sp)
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; CHECK-NEXT: lw ra, 28(sp)
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; CHECK-NEXT: addi sp, sp, 32
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; CHECK-NEXT: ret
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;
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; CHECK-LABEL: OUTLINED_FUNCTION_0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sw a0, -16(s0)
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; CHECK-NEXT: addi a0, zero, 2
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; CHECK-NEXT: sw a0, -20(s0)
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; CHECK-NEXT: addi a0, zero, 3
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; CHECK-NEXT: sw a0, -24(s0)
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; CHECK-NEXT: addi a0, zero, 4
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; CHECK-NEXT: sw a0, -28(s0)
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; CHECK-NEXT: jr t0
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@ -1,131 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -enable-machine-outliner -mtriple=riscv32-unknown-linux < %s | FileCheck %s
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@x = global i32 0, align 4
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define i32 @check_boundaries() #0 {
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; CHECK-LABEL: check_boundaries:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -32
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: sw ra, 28(sp)
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; CHECK-NEXT: sw s0, 24(sp)
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; CHECK-NEXT: .cfi_offset ra, -4
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; CHECK-NEXT: .cfi_offset s0, -8
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; CHECK-NEXT: addi s0, sp, 32
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; CHECK-NEXT: .cfi_def_cfa s0, 0
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; CHECK-NEXT: sw zero, -12(s0)
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; CHECK-NEXT: sw zero, -16(s0)
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; CHECK-NEXT: addi a0, zero, 1
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; CHECK-NEXT: beqz zero, .LBB0_3
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: sw a0, -24(s0)
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; CHECK-NEXT: lw a0, -16(s0)
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; CHECK-NEXT: beqz a0, .LBB0_4
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: addi a0, zero, 1
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; CHECK-NEXT: sw a0, -24(s0)
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; CHECK-NEXT: j .LBB0_5
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; CHECK-NEXT: .LBB0_3:
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; CHECK-NEXT: call t0, OUTLINED_FUNCTION_0
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; CHECK-NEXT: lw a0, -16(s0)
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; CHECK-NEXT: bnez a0, .LBB0_2
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; CHECK-NEXT: .LBB0_4:
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; CHECK-NEXT: addi a0, zero, 1
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; CHECK-NEXT: call t0, OUTLINED_FUNCTION_0
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; CHECK-NEXT: .LBB0_5:
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; CHECK-NEXT: mv a0, zero
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; CHECK-NEXT: lw s0, 24(sp)
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; CHECK-NEXT: lw ra, 28(sp)
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; CHECK-NEXT: addi sp, sp, 32
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; CHECK-NEXT: ret
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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%3 = alloca i32, align 4
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%4 = alloca i32, align 4
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%5 = alloca i32, align 4
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store i32 0, i32* %1, align 4
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store i32 0, i32* %2, align 4
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%6 = load i32, i32* %2, align 4
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%7 = icmp ne i32 %6, 0
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br i1 %7, label %9, label %8
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store i32 1, i32* %2, align 4
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store i32 2, i32* %3, align 4
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store i32 3, i32* %4, align 4
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store i32 4, i32* %5, align 4
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br label %10
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store i32 1, i32* %4, align 4
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br label %10
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%11 = load i32, i32* %2, align 4
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%12 = icmp ne i32 %11, 0
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br i1 %12, label %14, label %13
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store i32 1, i32* %2, align 4
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store i32 2, i32* %3, align 4
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store i32 3, i32* %4, align 4
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store i32 4, i32* %5, align 4
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br label %15
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store i32 1, i32* %4, align 4
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br label %15
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ret i32 0
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}
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define i32 @main() #0 {
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; CHECK-LABEL: main:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -32
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: sw ra, 28(sp)
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; CHECK-NEXT: sw s0, 24(sp)
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; CHECK-NEXT: .cfi_offset ra, -4
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; CHECK-NEXT: .cfi_offset s0, -8
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; CHECK-NEXT: addi s0, sp, 32
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; CHECK-NEXT: .cfi_def_cfa s0, 0
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; CHECK-NEXT: sw zero, -12(s0)
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; CHECK-NEXT: lui a0, %hi(x)
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; CHECK-NEXT: addi a1, zero, 1
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; CHECK-NEXT: sw a1, -16(s0)
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; CHECK-NEXT: addi a2, zero, 2
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; CHECK-NEXT: sw a2, -20(s0)
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; CHECK-NEXT: addi a3, zero, 3
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; CHECK-NEXT: sw a3, -24(s0)
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; CHECK-NEXT: addi a4, zero, 4
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; CHECK-NEXT: sw a4, -28(s0)
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; CHECK-NEXT: sw a1, %lo(x)(a0)
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; CHECK-NEXT: #APP
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: sw a1, -16(s0)
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; CHECK-NEXT: sw a2, -20(s0)
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; CHECK-NEXT: sw a3, -24(s0)
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; CHECK-NEXT: sw a4, -28(s0)
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; CHECK-NEXT: mv a0, zero
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; CHECK-NEXT: lw s0, 24(sp)
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; CHECK-NEXT: lw ra, 28(sp)
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; CHECK-NEXT: addi sp, sp, 32
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; CHECK-NEXT: ret
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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%3 = alloca i32, align 4
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%4 = alloca i32, align 4
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%5 = alloca i32, align 4
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store i32 0, i32* %1, align 4
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store i32 0, i32* @x, align 4
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store i32 1, i32* %2, align 4
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store i32 2, i32* %3, align 4
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store i32 3, i32* %4, align 4
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store i32 4, i32* %5, align 4
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store i32 1, i32* @x, align 4
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call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
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store i32 1, i32* %2, align 4
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store i32 2, i32* %3, align 4
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store i32 3, i32* %4, align 4
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store i32 4, i32* %5, align 4
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ret i32 0
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}
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attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
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@ -1,17 +0,0 @@
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# REQUIRES: riscv-registered-target
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## Check that generated functions are included.
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# RUN: cp -f %S/Inputs/riscv_generated_funcs.ll %t.ll && %update_llc_test_checks --include-generated-funcs %t.ll
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# RUN: diff -u %t.ll %S/Inputs/riscv_generated_funcs.ll.generated.expected
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## Check that running the script again does not change the result:
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# RUN: %update_llc_test_checks --include-generated-funcs %t.ll
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# RUN: diff -u %t.ll %S/Inputs/riscv_generated_funcs.ll.generated.expected
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## Check that generated functions are not included.
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# RUN: cp -f %S/Inputs/riscv_generated_funcs.ll %t.ll && %update_llc_test_checks %t.ll
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# RUN: diff -u %t.ll %S/Inputs/riscv_generated_funcs.ll.nogenerated.expected
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## Check that running the script again does not change the result:
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# RUN: %update_llc_test_checks %t.ll
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# RUN: diff -u %t.ll %S/Inputs/riscv_generated_funcs.ll.nogenerated.expected
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