forked from OSchip/llvm-project
[AArch64][GlobalISel] Change G_FCONSTANTs feeding into stores into G_CONSTANTS
Given the following situation: x = G_FCONSTANT (something that can't be materialized) G_STORE x, some_addr We know that x must be materialized as at least a single mov. However, at the time of selection, the G_STORE will have been regbankselected to a FPR store. So, as a result, you'll get an unnecessary fmov into the G_STORE. Storing a constant value in a GPR and a constant value in a FPR are the same. So, whenever you see a G_FCONSTANT that feeds into only G_STORES, so might as well make it a G_CONSTANT. This adds a target-specific combine which changes G_FCONSTANTs feeding into G_STOREs into G_CONSTANTs. Differential Revision: https://reviews.llvm.org/D72814
This commit is contained in:
Jessica Paquette
parent
25b542c61f
commit
b82d18e1e8
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@ -11,8 +11,15 @@
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include "llvm/Target/GlobalISel/Combine.td"
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def fconstant_to_constant : GICombineRule<
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(defs root:$root),
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(match (wip_match_opcode G_FCONSTANT):$root,
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[{ return matchFConstantToConstant(*${root}, MRI); }]),
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(apply [{ applyFConstantToConstant(*${root}); }])>;
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def AArch64PreLegalizerCombinerHelper: GICombinerHelper<
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"AArch64GenPreLegalizerCombinerHelper", [all_combines,
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elide_br_by_inverting_cond]> {
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elide_br_by_inverting_cond,
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fconstant_to_constant]> {
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let DisableRuleOption = "aarch64prelegalizercombiner-disable-rule";
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}
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@ -27,6 +27,32 @@
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using namespace llvm;
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using namespace MIPatternMatch;
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/// Return true if a G_FCONSTANT instruction is known to be better-represented
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/// as a G_CONSTANT.
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static bool matchFConstantToConstant(MachineInstr &MI,
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MachineRegisterInfo &MRI) {
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assert(MI.getOpcode() == TargetOpcode::G_FCONSTANT);
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Register DstReg = MI.getOperand(0).getReg();
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const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
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if (DstSize != 32 && DstSize != 64)
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return false;
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// When we're storing a value, it doesn't matter what register bank it's on.
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// Since not all floating point constants can be materialized using a fmov,
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// it makes more sense to just use a GPR.
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return all_of(MRI.use_instructions(DstReg),
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[](const MachineInstr &Use) { return Use.mayStore(); });
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}
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/// Change a G_FCONSTANT into a G_CONSTANT.
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static void applyFConstantToConstant(MachineInstr &MI) {
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assert(MI.getOpcode() == TargetOpcode::G_FCONSTANT);
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MachineIRBuilder MIB(MI);
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const APFloat &ImmValAPF = MI.getOperand(1).getFPImm()->getValueAPF();
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MIB.buildConstant(MI.getOperand(0).getReg(), ImmValAPF.bitcastToAPInt());
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MI.eraseFromParent();
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}
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#define AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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#include "AArch64GenGICombiner.inc"
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#undef AARCH64PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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@ -0,0 +1,73 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
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...
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---
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name: fconstant_to_constant_s32
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x0
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; Only feeding into stores here. Also, the value can't be materialized using
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; fmov, so it's strictly better to use a mov.
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; CHECK-LABEL: name: fconstant_to_constant_s32
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; CHECK: liveins: $x0
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; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1028443341
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; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 524
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; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
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; CHECK: G_STORE [[C]](s32), [[PTR_ADD]](p0) :: (store 4)
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; CHECK: RET_ReallyLR
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%0:_(p0) = COPY $x0
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%3:_(s32) = G_FCONSTANT float 0x3FA99999A0000000
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%1:_(s64) = G_CONSTANT i64 524
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%2:_(p0) = G_PTR_ADD %0, %1(s64)
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G_STORE %3(s32), %2(p0) :: (store 4)
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RET_ReallyLR
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...
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---
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name: fconstant_to_constant_s64
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x0
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; CHECK-LABEL: name: fconstant_to_constant_s64
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; CHECK: liveins: $x0
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; CHECK: %ptr:_(p0) = COPY $x0
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; CHECK: %c:_(s64) = G_CONSTANT i64 0
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; CHECK: G_STORE %c(s64), %ptr(p0) :: (store 8)
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; CHECK: RET_ReallyLR
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%ptr:_(p0) = COPY $x0
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%c:_(s64) = G_FCONSTANT double 0.0
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G_STORE %c(s64), %ptr(p0) :: (store 8)
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RET_ReallyLR
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...
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---
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name: no_store_means_no_combine
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x0, $x1
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; When we aren't feeding into a store, the combine shouldn't happen.
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; CHECK-LABEL: name: no_store_means_no_combine
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; CHECK: liveins: $x0, $x1
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; CHECK: %v:_(s64) = COPY $x0
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; CHECK: %c:_(s64) = G_FCONSTANT double 0.000000e+00
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; CHECK: %add:_(s64) = G_FADD %v, %c
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; CHECK: RET_ReallyLR implicit %add(s64)
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%v:_(s64) = COPY $x0
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%c:_(s64) = G_FCONSTANT double 0.0
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%add:_(s64) = G_FADD %v, %c
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RET_ReallyLR implicit %add
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...
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