forked from OSchip/llvm-project
[GISel] Add new combines for G_ADD
Patch adds new GICombineRules for G_ADD: G_ADD(x, G_SUB(y, x)) -> y G_ADD(G_SUB(y, x), x) -> y Patch additionally adds new combine tests for AArch64 target for these new rules. Reviewed by: paquette Differential Revision: https://reviews.llvm.org/D87936
This commit is contained in:
Michael Kitzan
parent
99069ab212
commit
b7fcf6632f
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@ -736,6 +736,10 @@ public:
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bool matchCombineFMinMaxNaN(MachineInstr &MI, unsigned &Info);
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/// Transform G_ADD(x, G_SUB(y, x)) to y.
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/// Transform G_ADD(G_SUB(y, x), x) to y.
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bool matchAddSubSameReg(MachineInstr &MI, Register &Src);
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private:
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/// Given a non-indexed load or store instruction \p MI, find an offset that
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/// can be usefully and legally folded into it as a post-indexing operation.
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@ -891,13 +891,21 @@ def combine_fsub_fpext_fneg_fmul_to_fmad_or_fma: GICombineRule<
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*${root}, ${info}); }]),
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(apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
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def combine_minmax_nan_matchinfo: GIDefMatchData<"unsigned">;
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def combine_minmax_nan: GICombineRule<
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(defs root:$root, combine_minmax_nan_matchinfo:$info),
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(defs root:$root, unsigned_matchinfo:$info),
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(match (wip_match_opcode G_FMINNUM, G_FMAXNUM, G_FMINIMUM, G_FMAXIMUM):$root,
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[{ return Helper.matchCombineFMinMaxNaN(*${root}, ${info}); }]),
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(apply [{ Helper.replaceSingleDefInstWithOperand(*${root}, ${info}); }])>;
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// Transform (add x, (sub y, x)) -> y
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// Transform (add (sub y, x), x) -> y
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def add_sub_reg: GICombineRule <
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(defs root:$root, register_matchinfo:$matchinfo),
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(match (wip_match_opcode G_ADD):$root,
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[{ return Helper.matchAddSubSameReg(*${root}, ${matchinfo}); }]),
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(apply [{ return Helper.replaceSingleDefInstWithReg(*${root},
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${matchinfo}); }])>;
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// FIXME: These should use the custom predicate feature once it lands.
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def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
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undef_to_negative_one,
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@ -913,7 +921,8 @@ def identity_combines : GICombineGroup<[select_same_val, right_identity_zero,
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binop_same_val, binop_left_to_zero,
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binop_right_to_zero, p2i_to_i2p,
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i2p_to_p2i, anyext_trunc_fold,
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fneg_fneg_fold, right_identity_one]>;
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fneg_fneg_fold, right_identity_one,
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add_sub_reg]>;
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def const_combines : GICombineGroup<[constant_fp_op, const_ptradd_to_i2p,
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overlapping_and, mulo_by_2, mulo_by_0,
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@ -5633,6 +5633,22 @@ bool CombinerHelper::matchCombineFMinMaxNaN(MachineInstr &MI,
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return MatchNaN(1) || MatchNaN(2);
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}
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bool CombinerHelper::matchAddSubSameReg(MachineInstr &MI, Register &Src) {
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assert(MI.getOpcode() == TargetOpcode::G_ADD && "Expected a G_ADD");
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Register LHS = MI.getOperand(1).getReg();
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Register RHS = MI.getOperand(2).getReg();
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// Helper lambda to check for opportunities for
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// A + (B - A) -> B
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// (B - A) + A -> B
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auto CheckFold = [&](Register MaybeSub, Register MaybeSameReg) {
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Register Reg;
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return mi_match(MaybeSub, MRI, m_GSub(m_Reg(Src), m_Reg(Reg))) &&
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Reg == MaybeSameReg;
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};
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return CheckFold(LHS, RHS) || CheckFold(RHS, LHS);
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}
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bool CombinerHelper::tryCombine(MachineInstr &MI) {
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if (tryCombineCopy(MI))
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return true;
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@ -0,0 +1,129 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
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---
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name: add_lhs_sub_reg
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: add_lhs_sub_reg
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%2:_(s32) = G_SUB %0, %1
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%3:_(s32) = G_ADD %2, %1
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$w0 = COPY %3
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...
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---
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name: add_lhs_sub_reg_wide
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: add_lhs_sub_reg_wide
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $q0
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; CHECK-NEXT: $q0 = COPY [[COPY]](s128)
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%0:_(s128) = COPY $q0
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%1:_(s128) = COPY $q1
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%2:_(s128) = G_SUB %0, %1
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%3:_(s128) = G_ADD %2, %1
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$q0 = COPY %3
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...
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---
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name: add_lhs_sub_reg_vec
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x0, $x1
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; CHECK-LABEL: name: add_lhs_sub_reg_vec
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; CHECK: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $x0
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; CHECK-NEXT: $x0 = COPY [[COPY]](<4 x s16>)
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%0:_(<4 x s16>) = COPY $x0
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%1:_(<4 x s16>) = COPY $x1
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%2:_(<4 x s16>) = G_SUB %0, %1
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%3:_(<4 x s16>) = G_ADD %2, %1
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$x0 = COPY %3
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...
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---
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name: add_rhs_sub_reg
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: add_rhs_sub_reg
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
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%0:_(s32) = COPY $w0
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%1:_(s32) = COPY $w1
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%2:_(s32) = G_SUB %0, %1
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%3:_(s32) = G_ADD %1, %2
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$w0 = COPY %3
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...
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---
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name: add_rhs_sub_reg_wide
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $q0, $q1
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; CHECK-LABEL: name: add_rhs_sub_reg_wide
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; CHECK: liveins: $q0, $q1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $q0
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; CHECK-NEXT: $q0 = COPY [[COPY]](s128)
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%0:_(s128) = COPY $q0
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%1:_(s128) = COPY $q1
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%2:_(s128) = G_SUB %0, %1
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%3:_(s128) = G_ADD %1, %2
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$q0 = COPY %3
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...
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---
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name: add_rhs_sub_reg_vec
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alignment: 4
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tracksRegLiveness: true
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x0, $x1
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; CHECK-LABEL: name: add_rhs_sub_reg_vec
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; CHECK: liveins: $x0, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $x0
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; CHECK-NEXT: $x0 = COPY [[COPY]](<4 x s16>)
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%0:_(<4 x s16>) = COPY $x0
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%1:_(<4 x s16>) = COPY $x1
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%2:_(<4 x s16>) = G_SUB %0, %1
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%3:_(<4 x s16>) = G_ADD %1, %2
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$x0 = COPY %3
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...
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