forked from OSchip/llvm-project
[X86] Begin removing matching of FROUND_CURRENT and FROUND_NO_EXC from isel tables.
Instead I plan to have dedicated nodes for FROUND_CURRENT and FROUND_NO_EXC. This patch starts with FADDS/FSUBS/FMULS/FDIVS/FMAXS/FMINS/FSQRTS. llvm-svn: 355799
This commit is contained in:
Craig Topper
parent
428dcd5c3f
commit
b7e6bfe579
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@ -21943,6 +21943,20 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(),
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Op.getOperand(1), Src2);
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}
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case INTR_TYPE_2OP_SAE: {
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SDValue Sae = Op.getOperand(3);
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unsigned Opc;
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if (isRoundModeCurDirection(Sae))
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Opc = IntrData->Opc0;
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else if (isRoundModeSAE(Sae))
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Opc = IntrData->Opc1;
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else
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return SDValue();
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return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
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Op.getOperand(2));
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}
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case INTR_TYPE_3OP:
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case INTR_TYPE_3OP_IMM8: {
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SDValue Src1 = Op.getOperand(1);
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@ -22053,6 +22067,23 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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Src2, RoundingMode),
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Mask, passThru, Subtarget, DAG);
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}
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case INTR_TYPE_SCALAR_MASK_SAE: {
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SDValue Src1 = Op.getOperand(1);
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SDValue Src2 = Op.getOperand(2);
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SDValue passThru = Op.getOperand(3);
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SDValue Mask = Op.getOperand(4);
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SDValue Sae = Op.getOperand(5);
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unsigned Opc;
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if (isRoundModeCurDirection(Sae))
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Opc = IntrData->Opc0;
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else if (isRoundModeSAE(Sae))
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Opc = IntrData->Opc1;
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else
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return SDValue();
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return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2),
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Mask, passThru, Subtarget, DAG);
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}
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case INTR_TYPE_SCALAR_MASK_RM: {
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assert(Op.getNumOperands() == 6 && "Unexpected number of operands");
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SDValue Src1 = Op.getOperand(1);
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@ -27516,12 +27547,12 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
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case X86ISD::FMAX: return "X86ISD::FMAX";
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case X86ISD::FMAXS: return "X86ISD::FMAXS";
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case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
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case X86ISD::FMAXS_RND: return "X86ISD::FMAX_RND";
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case X86ISD::FMAX_SAE: return "X86ISD::FMAX_SAE";
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case X86ISD::FMAXS_SAE: return "X86ISD::FMAXS_SAE";
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case X86ISD::FMIN: return "X86ISD::FMIN";
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case X86ISD::FMINS: return "X86ISD::FMINS";
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case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
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case X86ISD::FMINS_RND: return "X86ISD::FMINS_RND";
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case X86ISD::FMIN_SAE: return "X86ISD::FMIN_SAE";
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case X86ISD::FMINS_SAE: return "X86ISD::FMINS_SAE";
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case X86ISD::FMAXC: return "X86ISD::FMAXC";
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case X86ISD::FMINC: return "X86ISD::FMINC";
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case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
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@ -27708,14 +27739,19 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
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case X86ISD::RSQRT28S: return "X86ISD::RSQRT28S";
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case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
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case X86ISD::FADDS: return "X86ISD::FADDS";
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case X86ISD::FADDS_RND: return "X86ISD::FADDS_RND";
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case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
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case X86ISD::FSUBS: return "X86ISD::FSUBS";
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case X86ISD::FSUBS_RND: return "X86ISD::FSUBS_RND";
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case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
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case X86ISD::FMULS: return "X86ISD::FMULS";
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case X86ISD::FMULS_RND: return "X86ISD::FMULS_RND";
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case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
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case X86ISD::FDIVS: return "X86ISD::FDIVS";
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case X86ISD::FDIVS_RND: return "X86ISD::FDIVS_RND";
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case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
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case X86ISD::FSQRTS: return "X86ISD::FSQRTS";
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case X86ISD::FSQRTS_RND: return "X86ISD::FSQRTS_RND";
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case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
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case X86ISD::FGETEXPS_RND: return "X86ISD::FGETEXPS_RND";
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@ -211,13 +211,13 @@ namespace llvm {
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ADDSUB,
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// FP vector ops with rounding mode.
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FADD_RND, FADDS_RND,
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FSUB_RND, FSUBS_RND,
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FMUL_RND, FMULS_RND,
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FDIV_RND, FDIVS_RND,
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FMAX_RND, FMAXS_RND,
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FMIN_RND, FMINS_RND,
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FSQRT_RND, FSQRTS_RND,
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FADD_RND, FADDS, FADDS_RND,
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FSUB_RND, FSUBS, FSUBS_RND,
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FMUL_RND, FMULS, FMULS_RND,
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FDIV_RND, FDIVS, FDIVS_RND,
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FMAX_SAE, FMAXS_SAE,
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FMIN_SAE, FMINS_SAE,
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FSQRT_RND, FSQRTS, FSQRTS_RND,
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// FP vector get exponent.
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FGETEXP_RND, FGETEXPS_RND,
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@ -5452,16 +5452,14 @@ multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
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defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_.VT (VecNode _.RC:$src1, _.RC:$src2,
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(i32 FROUND_CURRENT)))>,
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(_.VT (VecNode _.RC:$src1, _.RC:$src2))>,
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Sched<[sched]>;
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defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(_.VT (VecNode _.RC:$src1,
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_.ScalarIntMemCPat:$src2,
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(i32 FROUND_CURRENT)))>,
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_.ScalarIntMemCPat:$src2))>,
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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let isCodeGenOnly = 1, Predicates = [HasAVX512] in {
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def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
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@ -5528,23 +5526,22 @@ multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
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defm rrb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr,
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"{sae}, $src2, $src1", "$src1, $src2, {sae}",
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(SaeNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
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(i32 FROUND_NO_EXC))>, EVEX_B,
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Sched<[sched]>;
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(SaeNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))>,
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EVEX_B, Sched<[sched]>;
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}
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}
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multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
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SDNode VecNode, X86SchedWriteSizes sched,
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bit IsCommutable> {
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SDNode VecNode, SDNode RndNode,
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X86SchedWriteSizes sched, bit IsCommutable> {
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defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
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sched.PS.Scl, IsCommutable>,
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avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
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avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, RndNode,
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sched.PS.Scl, IsCommutable>,
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XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
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defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
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sched.PD.Scl, IsCommutable>,
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avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
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avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, RndNode,
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sched.PD.Scl, IsCommutable>,
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XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
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}
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@ -5559,17 +5556,17 @@ multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
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VecNode, SaeNode, sched.PD.Scl, IsCommutable>,
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XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
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}
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defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnds,
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defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86fadds, X86faddRnds,
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SchedWriteFAddSizes, 1>;
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defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnds,
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defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmuls, X86fmulRnds,
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SchedWriteFMulSizes, 1>;
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defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnds,
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defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubs, X86fsubRnds,
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SchedWriteFAddSizes, 0>;
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defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnds,
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defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivs, X86fdivRnds,
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SchedWriteFDivSizes, 0>;
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defm VMIN : avx512_binop_s_sae<0x5D, "vmin", X86fmin, X86fmins, X86fminRnds,
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defm VMIN : avx512_binop_s_sae<0x5D, "vmin", X86fmin, X86fmins, X86fminSAEs,
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SchedWriteFCmpSizes, 0>;
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defm VMAX : avx512_binop_s_sae<0x5F, "vmax", X86fmax, X86fmaxs, X86fmaxRnds,
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defm VMAX : avx512_binop_s_sae<0x5F, "vmax", X86fmax, X86fmaxs, X86fmaxSAEs,
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SchedWriteFCmpSizes, 0>;
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// MIN/MAX nodes are commutable under "unsafe-fp-math". In this case we use
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@ -5656,7 +5653,7 @@ multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr,
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defm rrb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
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"{sae}, $src2, $src1", "$src1, $src2, {sae}",
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(_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
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(_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2))>,
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EVEX_4V, EVEX_B, Sched<[sched]>;
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}
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@ -5725,10 +5722,10 @@ defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv, HasAVX512,
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avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd, SchedWriteFDivSizes>;
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defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, HasAVX512,
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SchedWriteFCmpSizes, 0>,
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avx512_fp_binop_p_sae<0x5D, "vmin", X86fminRnd, SchedWriteFCmpSizes>;
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avx512_fp_binop_p_sae<0x5D, "vmin", X86fminSAE, SchedWriteFCmpSizes>;
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defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, HasAVX512,
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SchedWriteFCmpSizes, 0>,
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avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxRnd, SchedWriteFCmpSizes>;
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avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxSAE, SchedWriteFCmpSizes>;
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let isCodeGenOnly = 1 in {
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defm VMINC : avx512_fp_binop_p<0x5D, "vmin", X86fminc, HasAVX512,
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SchedWriteFCmpSizes, 1>;
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@ -9317,16 +9314,14 @@ multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr, X86FoldableSchedWri
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defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(X86fsqrtRnds (_.VT _.RC:$src1),
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(_.VT _.RC:$src2),
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(i32 FROUND_CURRENT))>,
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(X86fsqrts (_.VT _.RC:$src1),
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(_.VT _.RC:$src2))>,
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Sched<[sched]>;
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defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(X86fsqrtRnds (_.VT _.RC:$src1),
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_.ScalarIntMemCPat:$src2,
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(i32 FROUND_CURRENT))>,
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(X86fsqrts (_.VT _.RC:$src1),
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_.ScalarIntMemCPat:$src2)>,
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
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@ -459,20 +459,25 @@ def X86Blendv : SDNode<"X86ISD::BLENDV",
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def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
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def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
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def X86fadds : SDNode<"X86ISD::FADDS", SDTFPBinOp>;
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def X86faddRnds : SDNode<"X86ISD::FADDS_RND", SDTFPBinOpRound>;
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def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
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def X86fsubs : SDNode<"X86ISD::FSUBS", SDTFPBinOp>;
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def X86fsubRnds : SDNode<"X86ISD::FSUBS_RND", SDTFPBinOpRound>;
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def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
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def X86fmuls : SDNode<"X86ISD::FMULS", SDTFPBinOp>;
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def X86fmulRnds : SDNode<"X86ISD::FMULS_RND", SDTFPBinOpRound>;
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def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
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def X86fdivs : SDNode<"X86ISD::FDIVS", SDTFPBinOp>;
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def X86fdivRnds : SDNode<"X86ISD::FDIVS_RND", SDTFPBinOpRound>;
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def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
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def X86fmaxRnds : SDNode<"X86ISD::FMAXS_RND", SDTFPBinOpRound>;
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def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
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def X86fminRnds : SDNode<"X86ISD::FMINS_RND", SDTFPBinOpRound>;
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def X86fmaxSAE : SDNode<"X86ISD::FMAX_SAE", SDTFPBinOp>;
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def X86fmaxSAEs : SDNode<"X86ISD::FMAXS_SAE", SDTFPBinOp>;
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def X86fminSAE : SDNode<"X86ISD::FMIN_SAE", SDTFPBinOp>;
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def X86fminSAEs : SDNode<"X86ISD::FMINS_SAE", SDTFPBinOp>;
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def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
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def X86scalefs : SDNode<"X86ISD::SCALEFS", SDTFPBinOpRound>;
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def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
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def X86fsqrts : SDNode<"X86ISD::FSQRTS", SDTFPBinOp>;
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def X86fsqrtRnds : SDNode<"X86ISD::FSQRTS_RND", SDTFPBinOpRound>;
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def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
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def X86fgetexpRnds : SDNode<"X86ISD::FGETEXPS_RND", SDTFPBinOpRound>;
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@ -24,10 +24,11 @@ enum IntrinsicType : uint16_t {
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INTR_TYPE_3OP_IMM8,
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CMP_MASK_CC,CMP_MASK_SCALAR_CC, VSHIFT, COMI, COMI_RM, BLENDV,
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CVTPD2PS_MASK,
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INTR_TYPE_2OP_SAE,
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INTR_TYPE_1OP_MASK, INTR_TYPE_1OP_MASK_RM,
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INTR_TYPE_2OP_MASK, INTR_TYPE_2OP_MASK_RM,
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INTR_TYPE_3OP_MASK,
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IFMA_OP, VPERM_2OP, INTR_TYPE_SCALAR_MASK,
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IFMA_OP, VPERM_2OP, INTR_TYPE_SCALAR_MASK, INTR_TYPE_SCALAR_MASK_SAE,
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INTR_TYPE_SCALAR_MASK_RM, INTR_TYPE_3OP_SCALAR_MASK,
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COMPRESS_EXPAND_IN_REG,
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TRUNCATE_TO_REG, CVTPS2PH_MASK, CVTPD2DQ_MASK, CVTQQ2PS_MASK,
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@ -456,10 +457,10 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx512_kadd_d, INTR_TYPE_2OP, X86ISD::KADD, 0),
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X86_INTRINSIC_DATA(avx512_kadd_q, INTR_TYPE_2OP, X86ISD::KADD, 0),
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X86_INTRINSIC_DATA(avx512_kadd_w, INTR_TYPE_2OP, X86ISD::KADD, 0),
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X86_INTRINSIC_DATA(avx512_mask_add_sd_round, INTR_TYPE_SCALAR_MASK_RM,
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X86ISD::FADDS_RND, 0),
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X86_INTRINSIC_DATA(avx512_mask_add_ss_round, INTR_TYPE_SCALAR_MASK_RM,
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X86ISD::FADDS_RND, 0),
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X86_INTRINSIC_DATA(avx512_mask_add_sd_round, INTR_TYPE_SCALAR_MASK,
|
||||
X86ISD::FADDS, X86ISD::FADDS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_add_ss_round, INTR_TYPE_SCALAR_MASK,
|
||||
X86ISD::FADDS, X86ISD::FADDS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cmp_sd, CMP_MASK_SCALAR_CC,
|
||||
X86ISD::FSETCCM, X86ISD::FSETCCM_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cmp_ss, CMP_MASK_SCALAR_CC,
|
||||
|
|
@ -569,10 +570,10 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
|||
X86ISD::CVTTP2UI, X86ISD::CVTTP2UI_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_cvtuqq2ps_128, CVTQQ2PS_MASK,
|
||||
X86ISD::CVTUI2P, X86ISD::MCVTUI2P),
|
||||
X86_INTRINSIC_DATA(avx512_mask_div_sd_round, INTR_TYPE_SCALAR_MASK_RM,
|
||||
X86ISD::FDIVS_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_div_ss_round, INTR_TYPE_SCALAR_MASK_RM,
|
||||
X86ISD::FDIVS_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_div_sd_round, INTR_TYPE_SCALAR_MASK,
|
||||
X86ISD::FDIVS, X86ISD::FDIVS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_div_ss_round, INTR_TYPE_SCALAR_MASK,
|
||||
X86ISD::FDIVS, X86ISD::FDIVS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_expand, COMPRESS_EXPAND_IN_REG,
|
||||
X86ISD::EXPAND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_fixupimm_pd_128, FIXUPIMM, X86ISD::VFIXUPIMM, 0),
|
||||
|
|
@ -617,18 +618,18 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
|||
X86ISD::VGETMANTS, X86ISD::VGETMANTS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_getmant_ss, INTR_TYPE_3OP_SCALAR_MASK,
|
||||
X86ISD::VGETMANTS, X86ISD::VGETMANTS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_max_sd_round, INTR_TYPE_SCALAR_MASK,
|
||||
X86ISD::FMAXS, X86ISD::FMAXS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_max_ss_round, INTR_TYPE_SCALAR_MASK,
|
||||
X86ISD::FMAXS, X86ISD::FMAXS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_min_sd_round, INTR_TYPE_SCALAR_MASK,
|
||||
X86ISD::FMINS, X86ISD::FMINS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_min_ss_round, INTR_TYPE_SCALAR_MASK,
|
||||
X86ISD::FMINS, X86ISD::FMINS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_mul_sd_round, INTR_TYPE_SCALAR_MASK_RM,
|
||||
X86ISD::FMULS_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_mul_ss_round, INTR_TYPE_SCALAR_MASK_RM,
|
||||
X86ISD::FMULS_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_max_sd_round, INTR_TYPE_SCALAR_MASK_SAE,
|
||||
X86ISD::FMAXS, X86ISD::FMAXS_SAE),
|
||||
X86_INTRINSIC_DATA(avx512_mask_max_ss_round, INTR_TYPE_SCALAR_MASK_SAE,
|
||||
X86ISD::FMAXS, X86ISD::FMAXS_SAE),
|
||||
X86_INTRINSIC_DATA(avx512_mask_min_sd_round, INTR_TYPE_SCALAR_MASK_SAE,
|
||||
X86ISD::FMINS, X86ISD::FMINS_SAE),
|
||||
X86_INTRINSIC_DATA(avx512_mask_min_ss_round, INTR_TYPE_SCALAR_MASK_SAE,
|
||||
X86ISD::FMINS, X86ISD::FMINS_SAE),
|
||||
X86_INTRINSIC_DATA(avx512_mask_mul_sd_round, INTR_TYPE_SCALAR_MASK,
|
||||
X86ISD::FMULS, X86ISD::FMULS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_mul_ss_round, INTR_TYPE_SCALAR_MASK,
|
||||
X86ISD::FMULS, X86ISD::FMULS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_pmov_db_128, TRUNCATE_TO_REG,
|
||||
X86ISD::VTRUNC, X86ISD::VMTRUNC),
|
||||
X86_INTRINSIC_DATA(avx512_mask_pmov_db_256, TRUNCATE_TO_REG,
|
||||
|
|
@ -771,14 +772,14 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
|||
X86ISD::SCALEFS, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_scalef_ss, INTR_TYPE_SCALAR_MASK_RM,
|
||||
X86ISD::SCALEFS, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_sqrt_sd, INTR_TYPE_SCALAR_MASK_RM,
|
||||
X86ISD::FSQRTS_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_sqrt_ss, INTR_TYPE_SCALAR_MASK_RM,
|
||||
X86ISD::FSQRTS_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_sub_sd_round, INTR_TYPE_SCALAR_MASK_RM,
|
||||
X86ISD::FSUBS_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_sub_ss_round, INTR_TYPE_SCALAR_MASK_RM,
|
||||
X86ISD::FSUBS_RND, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_sqrt_sd, INTR_TYPE_SCALAR_MASK,
|
||||
X86ISD::FSQRTS, X86ISD::FSQRTS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_sqrt_ss, INTR_TYPE_SCALAR_MASK,
|
||||
X86ISD::FSQRTS, X86ISD::FSQRTS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_sub_sd_round, INTR_TYPE_SCALAR_MASK,
|
||||
X86ISD::FSUBS, X86ISD::FSUBS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_sub_ss_round, INTR_TYPE_SCALAR_MASK,
|
||||
X86ISD::FSUBS, X86ISD::FSUBS_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mask_vcvtph2ps_128, INTR_TYPE_1OP_MASK,
|
||||
X86ISD::CVTPH2PS, 0),
|
||||
X86_INTRINSIC_DATA(avx512_mask_vcvtph2ps_256, INTR_TYPE_1OP_MASK,
|
||||
|
|
@ -809,10 +810,10 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
|||
X86_INTRINSIC_DATA(avx512_maskz_fixupimm_ss, FIXUPIMMS_MASKZ,
|
||||
X86ISD::VFIXUPIMMS, 0),
|
||||
|
||||
X86_INTRINSIC_DATA(avx512_max_pd_512, INTR_TYPE_2OP, X86ISD::FMAX, X86ISD::FMAX_RND),
|
||||
X86_INTRINSIC_DATA(avx512_max_ps_512, INTR_TYPE_2OP, X86ISD::FMAX, X86ISD::FMAX_RND),
|
||||
X86_INTRINSIC_DATA(avx512_min_pd_512, INTR_TYPE_2OP, X86ISD::FMIN, X86ISD::FMIN_RND),
|
||||
X86_INTRINSIC_DATA(avx512_min_ps_512, INTR_TYPE_2OP, X86ISD::FMIN, X86ISD::FMIN_RND),
|
||||
X86_INTRINSIC_DATA(avx512_max_pd_512, INTR_TYPE_2OP_SAE, X86ISD::FMAX, X86ISD::FMAX_SAE),
|
||||
X86_INTRINSIC_DATA(avx512_max_ps_512, INTR_TYPE_2OP_SAE, X86ISD::FMAX, X86ISD::FMAX_SAE),
|
||||
X86_INTRINSIC_DATA(avx512_min_pd_512, INTR_TYPE_2OP_SAE, X86ISD::FMIN, X86ISD::FMIN_SAE),
|
||||
X86_INTRINSIC_DATA(avx512_min_ps_512, INTR_TYPE_2OP_SAE, X86ISD::FMIN, X86ISD::FMIN_SAE),
|
||||
X86_INTRINSIC_DATA(avx512_mul_pd_512, INTR_TYPE_2OP, ISD::FMUL, X86ISD::FMUL_RND),
|
||||
X86_INTRINSIC_DATA(avx512_mul_ps_512, INTR_TYPE_2OP, ISD::FMUL, X86ISD::FMUL_RND),
|
||||
X86_INTRINSIC_DATA(avx512_packssdw_512, INTR_TYPE_2OP, X86ISD::PACKSS, 0),
|
||||
|
|
|
|||
Loading…
Reference in New Issue