From b7d3311c77f5785ebf6e4749a7ad1ec00381570e Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Sat, 6 Aug 2016 11:13:10 +0000 Subject: [PATCH] Move helpers into anonymous namespaces. NFC. llvm-svn: 277916 --- llvm/lib/CodeGen/AsmPrinter/AddressPool.cpp | 2 -- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 2 +- llvm/lib/CodeGen/LiveRegMatrix.cpp | 7 ++++--- llvm/lib/CodeGen/MachinePipeliner.cpp | 5 +++-- llvm/lib/CodeGen/RegisterUsageInfo.cpp | 2 +- llvm/lib/CodeGen/ShrinkWrap.cpp | 4 ++-- llvm/lib/IR/Verifier.cpp | 8 +++----- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp | 3 ++- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 2 ++ llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 2 ++ llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp | 2 ++ llvm/lib/Target/X86/X86OptimizeLEAs.cpp | 10 ++++------ llvm/lib/Transforms/Utils/Local.cpp | 2 ++ llvm/lib/Transforms/Utils/NameAnonFunctions.cpp | 2 ++ llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 3 ++- 15 files changed, 32 insertions(+), 24 deletions(-) diff --git a/llvm/lib/CodeGen/AsmPrinter/AddressPool.cpp b/llvm/lib/CodeGen/AsmPrinter/AddressPool.cpp index 8c6838394ac9..ec552e0640e9 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AddressPool.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AddressPool.cpp @@ -14,8 +14,6 @@ using namespace llvm; -class MCExpr; - unsigned AddressPool::getIndex(const MCSymbol *Sym, bool TLS) { HasBeenUsed = true; auto IterBool = diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp index 7fba7688f7fb..41d86050e548 100644 --- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp @@ -349,7 +349,7 @@ bool DwarfDebug::isLexicalScopeDIENull(LexicalScope *Scope) { return !getLabelAfterInsn(Ranges.front().second); } -template void forBothCUs(DwarfCompileUnit &CU, Func F) { +template static void forBothCUs(DwarfCompileUnit &CU, Func F) { F(CU); if (auto *SkelCU = CU.getSkeleton()) F(*SkelCU); diff --git a/llvm/lib/CodeGen/LiveRegMatrix.cpp b/llvm/lib/CodeGen/LiveRegMatrix.cpp index 7ee87c1e650f..088a92d162b3 100644 --- a/llvm/lib/CodeGen/LiveRegMatrix.cpp +++ b/llvm/lib/CodeGen/LiveRegMatrix.cpp @@ -70,9 +70,10 @@ void LiveRegMatrix::releaseMemory() { } } -template -bool foreachUnit(const TargetRegisterInfo *TRI, LiveInterval &VRegInterval, - unsigned PhysReg, Callable Func) { +template +static bool foreachUnit(const TargetRegisterInfo *TRI, + LiveInterval &VRegInterval, unsigned PhysReg, + Callable Func) { if (VRegInterval.hasSubRanges()) { for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { unsigned Unit = (*Units).first; diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index 922c5bf7384b..2246a83811fa 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -98,8 +98,9 @@ STATISTIC(NumTrytoPipeline, "Number of loops that we attempt to pipeline"); STATISTIC(NumPipelined, "Number of loops software pipelined"); /// A command line option to turn software pipelining on or off. -cl::opt EnableSWP("enable-pipeliner", cl::Hidden, cl::init(true), - cl::ZeroOrMore, cl::desc("Enable Software Pipelining")); +static cl::opt EnableSWP("enable-pipeliner", cl::Hidden, cl::init(true), + cl::ZeroOrMore, + cl::desc("Enable Software Pipelining")); /// A command line option to enable SWP at -Os. static cl::opt EnableSWPOptSize("enable-pipeliner-opt-size", diff --git a/llvm/lib/CodeGen/RegisterUsageInfo.cpp b/llvm/lib/CodeGen/RegisterUsageInfo.cpp index 5cf3e57eb3d3..66f196678dea 100644 --- a/llvm/lib/CodeGen/RegisterUsageInfo.cpp +++ b/llvm/lib/CodeGen/RegisterUsageInfo.cpp @@ -22,7 +22,7 @@ using namespace llvm; #define DEBUG_TYPE "ip-regalloc" -cl::opt DumpRegUsage( +static cl::opt DumpRegUsage( "print-regusage", cl::init(false), cl::Hidden, cl::desc("print register usage details collected for analysis.")); diff --git a/llvm/lib/CodeGen/ShrinkWrap.cpp b/llvm/lib/CodeGen/ShrinkWrap.cpp index d8e9df1e39fb..599fd87bfd1b 100644 --- a/llvm/lib/CodeGen/ShrinkWrap.cpp +++ b/llvm/lib/CodeGen/ShrinkWrap.cpp @@ -256,8 +256,8 @@ bool ShrinkWrap::useOrDefCSROrFI(const MachineInstr &MI, /// \brief Helper function to find the immediate (post) dominator. template -MachineBasicBlock *FindIDom(MachineBasicBlock &Block, ListOfBBs BBs, - DominanceAnalysis &Dom) { +static MachineBasicBlock *FindIDom(MachineBasicBlock &Block, ListOfBBs BBs, + DominanceAnalysis &Dom) { MachineBasicBlock *IDom = &Block; for (MachineBasicBlock *BB : BBs) { IDom = Dom.findNearestCommonDominator(IDom, BB); diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index 051404031161..4e1b4e1bbc53 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -762,7 +762,7 @@ static bool isScope(const Metadata *MD) { return !MD || isa(MD); } static bool isDINode(const Metadata *MD) { return !MD || isa(MD); } template -bool isValidMetadataArrayImpl(const MDTuple &N, bool AllowNull) { +static bool isValidMetadataArrayImpl(const MDTuple &N, bool AllowNull) { for (Metadata *MD : N.operands()) { if (MD) { if (!isa(MD)) @@ -775,13 +775,11 @@ bool isValidMetadataArrayImpl(const MDTuple &N, bool AllowNull) { return true; } -template -bool isValidMetadataArray(const MDTuple &N) { +template static bool isValidMetadataArray(const MDTuple &N) { return isValidMetadataArrayImpl(N, /* AllowNull */ false); } -template -bool isValidMetadataNullArray(const MDTuple &N) { +template static bool isValidMetadataNullArray(const MDTuple &N) { return isValidMetadataArrayImpl(N, /* AllowNull */ true); } diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index e579eba5829c..77c326dc3902 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -869,7 +869,7 @@ static bool produceCompactUnwindFrame(MachineFunction &MF) { Attrs.hasAttrSomewhere(Attribute::SwiftError)); } - +namespace { struct RegPairInfo { RegPairInfo() : Reg1(AArch64::NoRegister), Reg2(AArch64::NoRegister) {} unsigned Reg1; @@ -879,6 +879,7 @@ struct RegPairInfo { bool IsGPR; bool isPaired() const { return Reg2 != AArch64::NoRegister; } }; +} // end anonymous namespace static void computeCalleeSaveRegisterPairs( MachineFunction &MF, const std::vector &CSI, diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index d3599537a9df..f93288c2bebd 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -1028,6 +1028,7 @@ static bool areCFlagsAliveInSuccessors(MachineBasicBlock *MBB) { return false; } +namespace { struct UsedNZCV { bool N; bool Z; @@ -1042,6 +1043,7 @@ struct UsedNZCV { return *this; } }; +} // end anonymous namespace /// Find a condition code used by the instruction. /// Returns AArch64CC::Invalid if either the instruction does not use condition diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 1bbfa96ec5bc..ad4aece29057 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -1583,6 +1583,7 @@ int HexagonDAGToDAGISel::getHeight(SDNode *N) { return RootHeights[N]; } +namespace { struct WeightedLeaf { SDValue Value; int Weight; @@ -1673,6 +1674,7 @@ public: LeafPrioQueue(unsigned Opcode) : HaveConst(false), Opcode(Opcode) { } }; +} // end anonymous namespace WeightedLeaf LeafPrioQueue::findSHL(uint64_t MaxAmount) { int ResultPos; diff --git a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp index 89f0a1c4dcbd..9ff9d93ea0c3 100644 --- a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp +++ b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp @@ -51,6 +51,7 @@ using namespace llvm; #define DEBUG_TYPE "misched" +namespace { class HexagonCallMutation : public ScheduleDAGMutation { public: void apply(ScheduleDAGInstrs *DAG) override; @@ -58,6 +59,7 @@ private: bool shouldTFRICallBind(const HexagonInstrInfo &HII, const SUnit &Inst1, const SUnit &Inst2) const; }; +} // end anonymous namespace // Check if a call and subsequent A2_tfrpi instructions should maintain // scheduling affinity. We are looking for the TFRI to be consumed in diff --git a/llvm/lib/Target/X86/X86OptimizeLEAs.cpp b/llvm/lib/Target/X86/X86OptimizeLEAs.cpp index 4da0fddda395..78827228ca32 100644 --- a/llvm/lib/Target/X86/X86OptimizeLEAs.cpp +++ b/llvm/lib/Target/X86/X86OptimizeLEAs.cpp @@ -44,12 +44,6 @@ static cl::opt STATISTIC(NumSubstLEAs, "Number of LEA instruction substitutions"); STATISTIC(NumRedundantLEAs, "Number of redundant LEA instructions removed"); -class MemOpKey; - -/// \brief Returns a hash table key based on memory operands of \p MI. The -/// number of the first memory operand of \p MI is specified through \p N. -static inline MemOpKey getMemOpKey(const MachineInstr &MI, unsigned N); - /// \brief Returns true if two machine operands are identical and they are not /// physical registers. static inline bool isIdenticalOp(const MachineOperand &MO1, @@ -63,6 +57,7 @@ static bool isSimilarDispOp(const MachineOperand &MO1, /// \brief Returns true if the instruction is LEA. static inline bool isLEA(const MachineInstr &MI); +namespace { /// A key based on instruction's memory operands. class MemOpKey { public: @@ -95,6 +90,7 @@ public: // Address' displacement operand. const MachineOperand *Disp; }; +} // end anonymous namespace /// Provide DenseMapInfo for MemOpKey. namespace llvm { @@ -168,6 +164,8 @@ template <> struct DenseMapInfo { }; } +/// \brief Returns a hash table key based on memory operands of \p MI. The +/// number of the first memory operand of \p MI is specified through \p N. static inline MemOpKey getMemOpKey(const MachineInstr &MI, unsigned N) { assert((isLEA(MI) || MI.mayLoadOrStore()) && "The instruction must be a LEA, a load or a store"); diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp index 3148bae292e6..987460bef9d5 100644 --- a/llvm/lib/Transforms/Utils/Local.cpp +++ b/llvm/lib/Transforms/Utils/Local.cpp @@ -1703,6 +1703,7 @@ bool llvm::callsGCLeafFunction(ImmutableCallSite CS) { return false; } +namespace { /// A potential constituent of a bitreverse or bswap expression. See /// collectBitParts for a fuller explanation. struct BitPart { @@ -1718,6 +1719,7 @@ struct BitPart { enum { Unset = -1 }; }; +} // end anonymous namespace /// Analyze the specified subexpression and see if it is capable of providing /// pieces of a bswap or bitreverse. The subexpression provides a potential diff --git a/llvm/lib/Transforms/Utils/NameAnonFunctions.cpp b/llvm/lib/Transforms/Utils/NameAnonFunctions.cpp index c4f3839d8482..6629ab85510b 100644 --- a/llvm/lib/Transforms/Utils/NameAnonFunctions.cpp +++ b/llvm/lib/Transforms/Utils/NameAnonFunctions.cpp @@ -19,6 +19,7 @@ using namespace llvm; +namespace { // Compute a "unique" hash for the module based on the name of the public // functions. class ModuleHasher { @@ -57,6 +58,7 @@ public: return TheHash; } }; +} // end anonymous namespace // Rename all the anon functions in the module bool llvm::nameUnamedFunctions(Module &M) { diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 1dcd33f8ee79..05ffa067f656 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -3942,7 +3942,7 @@ static Value *createRdxShuffleMask(unsigned VecLen, unsigned NumEltsToRdx, return ConstantVector::get(ShuffleMask); } - +namespace { /// Model horizontal reductions. /// /// A horizontal reduction is a tree of reduction operations (currently add and @@ -4228,6 +4228,7 @@ private: return Builder.CreateExtractElement(TmpVec, Builder.getInt32(0)); } }; +} // end anonymous namespace /// \brief Recognize construction of vectors like /// %ra = insertelement <4 x float> undef, float %s0, i32 0