forked from OSchip/llvm-project
Revert "[AMDGPU] Fix DPP combiner"
This reverts commit e3e2923a39cbec3b3bc3a7d3f0e9a77a4115080e, svn revision rL350721 llvm-svn: 350730
This commit is contained in:
Valery Pykhtin
parent
c650ff77eb
commit
b7a459547d
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@ -429,13 +429,6 @@ public:
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RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
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: Reg(Reg), SubReg(SubReg) {}
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bool operator==(const RegSubRegPair& P) const {
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return Reg == P.Reg && SubReg == P.SubReg;
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}
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bool operator!=(const RegSubRegPair& P) const {
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return !(*this == P);
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}
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};
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/// A pair composed of a pair of a register and a sub-register index,
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@ -7,39 +7,31 @@
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//
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//===----------------------------------------------------------------------===//
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// The pass combines V_MOV_B32_dpp instruction with its VALU uses as a DPP src0
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// operand. If any of the use instruction cannot be combined with the mov the
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// operand.If any of the use instruction cannot be combined with the mov the
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// whole sequence is reverted.
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//
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// $old = ...
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// $dpp_value = V_MOV_B32_dpp $old, $vgpr_to_be_read_from_other_lane,
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// dpp_controls..., $row_mask, $bank_mask, $bound_ctrl
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// $res = VALU $dpp_value [, src1]
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// dpp_controls..., $bound_ctrl
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// $res = VALU $dpp_value, ...
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//
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// to
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//
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// $res = VALU_DPP $combined_old, $vgpr_to_be_read_from_other_lane, [src1,]
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// dpp_controls..., $row_mask, $bank_mask, $combined_bound_ctrl
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// $res = VALU_DPP $folded_old, $vgpr_to_be_read_from_other_lane, ...,
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// dpp_controls..., $folded_bound_ctrl
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//
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// Combining rules :
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//
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// if $row_mask and $bank_mask are fully enabled (0xF) and
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// $old == $vgpr_to_be_read_from_other_lane
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// -> $combined_old = undef
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// $combined_bound_ctrl = $bound_ctrl
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// $bound_ctrl is DPP_BOUND_ZERO, $old is any
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// $bound_ctrl is DPP_BOUND_OFF, $old is 0
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//
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// if $row_mask and $bank_mask are fully enabled (0xF) and
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// $bound_ctrl==DPP_BOUND_ZERO and $old==any or
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// $bound_ctrl==DPP_BOUND_OFF and $old==0 (immediate)
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// -> $combined_old = undef,
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// $combined_bound_ctrl = DPP_BOUND_ZERO
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// ->$folded_old = undef, $folded_bound_ctrl = DPP_BOUND_ZERO
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// $bound_ctrl is DPP_BOUND_OFF, $old is undef
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//
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// if the VALU op is binary and
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// ($old == 0(immediate) or $bound_ctrl==DPP_BOUND_OFF) and
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// $old==identity value (immediate) for the VALU op
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// -> $combined_old = src1,
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// $combined_bound_ctrl = DPP_BOUND_OFF
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// ->$folded_old = undef, $folded_bound_ctrl = DPP_BOUND_OFF
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// $bound_ctrl is DPP_BOUND_OFF, $old is foldable
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//
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// Othervise cancel.
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// ->$folded_old = folded value, $folded_bound_ctrl = DPP_BOUND_OFF
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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@ -75,6 +67,10 @@ class GCNDPPCombine : public MachineFunctionPass {
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MachineOperand *getOldOpndValue(MachineOperand &OldOpnd) const;
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RegSubRegPair foldOldOpnd(MachineInstr &OrigMI,
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RegSubRegPair OldOpndVGPR,
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MachineOperand &OldOpndValue) const;
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MachineInstr *createDPPInst(MachineInstr &OrigMI,
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MachineInstr &MovMI,
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RegSubRegPair OldOpndVGPR,
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@ -185,12 +181,6 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
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assert(isOfRegClass(OldOpndVGPR, AMDGPU::VGPR_32RegClass, *MRI));
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DPPInst.addReg(OldOpndVGPR.Reg, 0, OldOpndVGPR.SubReg);
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++NumOperands;
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} else {
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// TODO: this discards MAC/FMA instructions for now, let's add it later
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LLVM_DEBUG(dbgs() << " failed: no old operand in DPP instruction,"
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" TBD\n");
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Fail = true;
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break;
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}
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if (auto *Mod0 = TII->getNamedOperand(OrigMI,
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@ -209,7 +199,6 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
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break;
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}
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DPPInst.add(*Src0);
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DPPInst->getOperand(NumOperands).setIsKill(false);
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++NumOperands;
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if (auto *Mod1 = TII->getNamedOperand(OrigMI,
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@ -253,61 +242,60 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
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return DPPInst.getInstr();
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}
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static bool isIdentityValue(unsigned OrigMIOp, MachineOperand *OldOpnd) {
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assert(OldOpnd->isImm());
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switch (OrigMIOp) {
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GCNDPPCombine::RegSubRegPair
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GCNDPPCombine::foldOldOpnd(MachineInstr &OrigMI,
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RegSubRegPair OldOpndVGPR,
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MachineOperand &OldOpndValue) const {
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assert(OldOpndValue.isImm());
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switch (OrigMI.getOpcode()) {
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default: break;
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case AMDGPU::V_ADD_U32_e32:
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case AMDGPU::V_ADD_I32_e32:
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case AMDGPU::V_OR_B32_e32:
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case AMDGPU::V_SUBREV_U32_e32:
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case AMDGPU::V_SUBREV_I32_e32:
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case AMDGPU::V_MIN_U32_e32:
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if (OldOpnd->getImm() == 0)
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return true;
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break;
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case AMDGPU::V_AND_B32_e32:
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case AMDGPU::V_MAX_U32_e32:
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if (OldOpnd->getImm() ==
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static_cast<int64_t>(std::numeric_limits<uint32_t>::max()))
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return true;
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if (OldOpndValue.getImm() == std::numeric_limits<uint32_t>::max())
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return OldOpndVGPR;
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break;
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case AMDGPU::V_MAX_I32_e32:
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if (OldOpnd->getImm() == std::numeric_limits<int32_t>::max())
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return true;
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if (OldOpndValue.getImm() == std::numeric_limits<int32_t>::max())
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return OldOpndVGPR;
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break;
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case AMDGPU::V_MIN_I32_e32:
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if (OldOpnd->getImm() == std::numeric_limits<int32_t>::min())
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return true;
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if (OldOpndValue.getImm() == std::numeric_limits<int32_t>::min())
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return OldOpndVGPR;
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break;
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case AMDGPU::V_MUL_I32_I24_e32:
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case AMDGPU::V_MUL_U32_U24_e32:
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if (OldOpnd->getImm() == 1)
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return true;
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if (OldOpndValue.getImm() == 1) {
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auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
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assert(Src1 && Src1->isReg());
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return getRegSubRegPair(*Src1);
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}
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break;
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}
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return false;
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return RegSubRegPair();
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}
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// Cases to combine:
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// $bound_ctrl is DPP_BOUND_ZERO, $old is any
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// $bound_ctrl is DPP_BOUND_OFF, $old is 0
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// -> $old = undef, $bound_ctrl = DPP_BOUND_ZERO
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// $bound_ctrl is DPP_BOUND_OFF, $old is undef
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// -> $old = undef, $bound_ctrl = DPP_BOUND_OFF
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// $bound_ctrl is DPP_BOUND_OFF, $old is foldable
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// -> $old = folded value, $bound_ctrl = DPP_BOUND_OFF
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MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
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MachineInstr &MovMI,
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RegSubRegPair OldOpndVGPR,
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MachineOperand *OldOpndValue,
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bool BoundCtrlZero) const {
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assert(OldOpndVGPR.Reg);
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if (!BoundCtrlZero && OldOpndValue && OldOpndValue->isImm()) {
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auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
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if (!Src1 || !Src1->isReg()) {
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LLVM_DEBUG(dbgs() << " failed: no src1 or it isn't a register\n");
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return nullptr;
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}
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if (!isIdentityValue(OrigMI.getOpcode(), OldOpndValue)) {
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LLVM_DEBUG(dbgs() << " failed: old immediate ins't an identity\n");
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return nullptr;
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}
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OldOpndVGPR = getRegSubRegPair(*Src1);
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if (!isOfRegClass(OldOpndVGPR, AMDGPU::VGPR_32RegClass, *MRI)) {
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LLVM_DEBUG(dbgs() << " failed: src1 isn't a VGPR32 register\n");
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if (!BoundCtrlZero && OldOpndValue) {
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assert(OldOpndValue->isImm());
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OldOpndVGPR = foldOldOpnd(OrigMI, OldOpndVGPR, *OldOpndValue);
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if (!OldOpndVGPR.Reg) {
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LLVM_DEBUG(dbgs() << " failed: old immediate cannot be folded\n");
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return nullptr;
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}
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}
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@ -328,97 +316,39 @@ bool GCNDPPCombine::hasNoImmOrEqual(MachineInstr &MI, unsigned OpndName,
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bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
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assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp);
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LLVM_DEBUG(dbgs() << "\nDPP combine: " << MovMI);
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auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);
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assert(DstOpnd && DstOpnd->isReg());
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auto DPPMovReg = DstOpnd->getReg();
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if (!isEXECMaskConstantBetweenDefAndUses(DPPMovReg, *MRI)) {
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LLVM_DEBUG(dbgs() << " failed: EXEC mask should remain the same"
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" for all uses\n");
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return false;
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}
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auto *RowMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask);
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assert(RowMaskOpnd && RowMaskOpnd->isImm());
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auto *BankMaskOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bank_mask);
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assert(BankMaskOpnd && BankMaskOpnd->isImm());
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const bool MaskAllLanes = RowMaskOpnd->getImm() == 0xF &&
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BankMaskOpnd->getImm() == 0xF;
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auto *BCZOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::bound_ctrl);
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assert(BCZOpnd && BCZOpnd->isImm());
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bool BoundCtrlZero = BCZOpnd->getImm();
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bool BoundCtrlZero = 0 != BCZOpnd->getImm();
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LLVM_DEBUG(dbgs() << "\nDPP combine: " << MovMI);
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auto *OldOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::old);
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assert(OldOpnd && OldOpnd->isReg());
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auto OldOpndVGPR = getRegSubRegPair(*OldOpnd);
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auto *OldOpndValue = getOldOpndValue(*OldOpnd);
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assert(!OldOpndValue || OldOpndValue->isImm() || OldOpndValue == OldOpnd);
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do {
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if (!OldOpndValue) { // undef case
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if (!BoundCtrlZero || !MaskAllLanes) {
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LLVM_DEBUG(dbgs()
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<< " failed: undef old has bctr off or mask isn't full BB\n");
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return false;
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}
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break;
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}
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if (BoundCtrlZero && MaskAllLanes) { // [1]
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OldOpndVGPR.Reg = AMDGPU::NoRegister;
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if (OldOpndValue) {
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if (BoundCtrlZero) {
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OldOpndVGPR.Reg = AMDGPU::NoRegister; // should be undef, ignore old opnd
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OldOpndValue = nullptr;
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break;
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}
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if (OldOpndValue->getParent()->getParent() != MovMI.getParent()) {
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LLVM_DEBUG(dbgs() <<
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" failed: old reg def and mov should be in the same BB\n");
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return false;
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}
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if (OldOpndValue->isImm()) {
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if (OldOpndValue->getImm() == 0) {
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if (MaskAllLanes) {
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assert(!BoundCtrlZero); // by check [1]
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// undefine old to make regalloc's life easier but this requires
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// bound_ctrl:0 set
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OldOpndVGPR.Reg = AMDGPU::NoRegister;
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OldOpndValue = nullptr;
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BoundCtrlZero = true;
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} else {
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// bound_ctrl value ins't important here but this makes the combiner's
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// logic easier - we check the VALU op for identity value when
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// BoundCtrlZero == false.
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BoundCtrlZero = false;
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}
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} else if (BoundCtrlZero) {
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assert(!MaskAllLanes); // by check [1]
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LLVM_DEBUG(dbgs() <<
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" failed: old!=0 and bctrl:0 and not all lanes isn't combinable\n");
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} else {
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if (!OldOpndValue->isImm()) {
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LLVM_DEBUG(dbgs() << " failed: old operand isn't an imm or undef\n");
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return false;
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}
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break;
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if (OldOpndValue->getImm() == 0) {
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OldOpndVGPR.Reg = AMDGPU::NoRegister; // should be undef
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OldOpndValue = nullptr;
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BoundCtrlZero = true;
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}
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}
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assert(OldOpndValue->isReg());
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auto *DPPSrcOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0);
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assert(DPPSrcOpnd && DPPSrcOpnd->isReg());
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if (!MaskAllLanes || getRegSubRegPair(*DPPSrcOpnd) != OldOpndVGPR) {
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LLVM_DEBUG(dbgs() << " failed: the DPP mov isn't combinable\n");
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return false;
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}
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// case when DPP mov old == DPP scr register
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OldOpndVGPR.Reg = AMDGPU::NoRegister;
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OldOpndValue = nullptr;
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} while (0);
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}
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LLVM_DEBUG(dbgs() << " old=";
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if (!OldOpndValue)
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dbgs() << "undef";
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else
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dbgs() << *OldOpndValue;
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dbgs() << OldOpndValue->getImm();
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dbgs() << ", bound_ctrl=" << BoundCtrlZero << '\n');
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std::vector<MachineInstr*> OrigMIs, DPPMIs;
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@ -432,12 +362,11 @@ bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
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OrigMIs.push_back(&MovMI);
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bool Rollback = true;
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for (auto &Use : MRI->use_nodbg_operands(DPPMovReg)) {
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for (auto &Use : MRI->use_nodbg_operands(
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TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg())) {
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Rollback = true;
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auto &OrigMI = *Use.getParent();
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LLVM_DEBUG(dbgs() << " try: " << OrigMI);
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auto OrigOp = OrigMI.getOpcode();
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if (TII->isVOP3(OrigOp)) {
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if (!TII->hasVALU32BitEncoding(OrigOp)) {
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@ -5591,29 +5591,3 @@ MachineInstr *llvm::getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P,
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}
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return nullptr;
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}
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bool llvm::isEXECMaskConstantBetweenDefAndUses(unsigned VReg,
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MachineRegisterInfo &MRI) {
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assert(MRI.isSSA() && "Must be run on SSA");
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auto *TRI = MRI.getTargetRegisterInfo();
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auto *DefI = MRI.getVRegDef(VReg);
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auto *BB = DefI->getParent();
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DenseSet<MachineInstr*> Uses;
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for (auto &Use : MRI.use_nodbg_operands(VReg)) {
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auto *I = Use.getParent();
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if (I->getParent() != BB)
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return false;
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Uses.insert(I);
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}
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auto E = BB->end();
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for (auto I = std::next(DefI->getIterator()); I != E; ++I) {
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Uses.erase(&*I);
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// don't check the last use
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if (Uses.empty() || I->modifiesRegister(AMDGPU::EXEC, TRI))
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break;
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}
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return Uses.empty();
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}
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@ -956,12 +956,6 @@ TargetInstrInfo::RegSubRegPair getRegSequenceSubReg(MachineInstr &MI,
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MachineInstr *getVRegSubRegDef(const TargetInstrInfo::RegSubRegPair &P,
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MachineRegisterInfo &MRI);
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/// \brief Return true if EXEC mask isnt' changed between the def and
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/// all uses of VReg. Currently if def and uses are in different BBs -
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/// simply return false. Should be run on SSA.
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bool isEXECMaskConstantBetweenDefAndUses(unsigned VReg,
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MachineRegisterInfo &MRI);
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namespace AMDGPU {
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LLVM_READONLY
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@ -0,0 +1,185 @@
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; RUN: llc -march=amdgcn -mcpu=tonga -amdgpu-dpp-combine -verify-machineinstrs < %s | FileCheck %s
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; VOP2 with literal cannot be combined
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; CHECK-LABEL: {{^}}dpp_combine_i32_literal:
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; CHECK: v_mov_b32_dpp [[OLD:v[0-9]+]], {{v[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x2 bank_mask:0x1 bound_ctrl:0
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; CHECK: v_add_u32_e32 {{v[0-9]+}}, vcc, 42, [[OLD]]
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define amdgpu_kernel void @dpp_combine_i32_literal(i32 addrspace(1)* %out, i32 %in) {
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%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 1, i32 2, i32 1, i1 1) #0
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%res = add nsw i32 %dpp, 42
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store i32 %res, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}dpp_combine_i32_bz:
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; CHECK: v_add_u32_dpp {{v[0-9]+}}, vcc, {{v[0-9]+}}, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
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define amdgpu_kernel void @dpp_combine_i32_bz(i32 addrspace(1)* %out, i32 %in) {
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%x = tail call i32 @llvm.amdgcn.workitem.id.x()
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%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 1, i32 1, i32 1, i1 1) #0
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||||
%res = add nsw i32 %dpp, %x
|
||||
store i32 %res, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}dpp_combine_i32_boff_undef:
|
||||
; CHECK: v_add_u32_dpp {{v[0-9]+}}, vcc, {{v[0-9]+}}, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
|
||||
define amdgpu_kernel void @dpp_combine_i32_boff_undef(i32 addrspace(1)* %out, i32 %in) {
|
||||
%x = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 1, i32 1, i32 1, i1 0) #0
|
||||
%res = add nsw i32 %dpp, %x
|
||||
store i32 %res, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}dpp_combine_i32_boff_0:
|
||||
; CHECK: v_add_u32_dpp {{v[0-9]+}}, vcc, {{v[0-9]+}}, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
|
||||
define amdgpu_kernel void @dpp_combine_i32_boff_0(i32 addrspace(1)* %out, i32 %in) {
|
||||
%x = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %in, i32 1, i32 1, i32 1, i1 0) #0
|
||||
%res = add nsw i32 %dpp, %x
|
||||
store i32 %res, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}dpp_combine_i32_boff_max:
|
||||
; CHECK: v_bfrev_b32_e32 [[OLD:v[0-9]+]], -2
|
||||
; CHECK: v_max_i32_dpp [[OLD]], {{v[0-9]+}}, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
|
||||
define amdgpu_kernel void @dpp_combine_i32_boff_max(i32 addrspace(1)* %out, i32 %in) {
|
||||
%x = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 2147483647, i32 %in, i32 1, i32 1, i32 1, i1 0) #0
|
||||
%cmp = icmp sge i32 %dpp, %x
|
||||
%res = select i1 %cmp, i32 %dpp, i32 %x
|
||||
store i32 %res, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}dpp_combine_i32_boff_min:
|
||||
; CHECK: v_bfrev_b32_e32 [[OLD:v[0-9]+]], 1
|
||||
; CHECK: v_min_i32_dpp [[OLD]], {{v[0-9]+}}, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
|
||||
define amdgpu_kernel void @dpp_combine_i32_boff_min(i32 addrspace(1)* %out, i32 %in) {
|
||||
%x = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 -2147483648, i32 %in, i32 1, i32 1, i32 1, i1 0) #0
|
||||
%cmp = icmp sle i32 %dpp, %x
|
||||
%res = select i1 %cmp, i32 %dpp, i32 %x
|
||||
store i32 %res, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}dpp_combine_i32_boff_mul:
|
||||
; CHECK: v_mul_i32_i24_dpp v0, v3, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
|
||||
define amdgpu_kernel void @dpp_combine_i32_boff_mul(i32 addrspace(1)* %out, i32 %in) {
|
||||
%x = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 1, i32 %in, i32 1, i32 1, i32 1, i1 0) #0
|
||||
|
||||
%dpp.shl = shl i32 %dpp, 8
|
||||
%dpp.24 = ashr i32 %dpp.shl, 8
|
||||
%x.shl = shl i32 %x, 8
|
||||
%x.24 = ashr i32 %x.shl, 8
|
||||
%res = mul i32 %dpp.24, %x.24
|
||||
store i32 %res, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}dpp_combine_i32_commute:
|
||||
; CHECK: v_subrev_u32_dpp {{v[0-9]+}}, vcc, {{v[0-9]+}}, v0 quad_perm:[2,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
|
||||
define amdgpu_kernel void @dpp_combine_i32_commute(i32 addrspace(1)* %out, i32 %in) {
|
||||
%x = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 2, i32 1, i32 1, i1 1) #0
|
||||
%res = sub nsw i32 %x, %dpp
|
||||
store i32 %res, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}dpp_combine_f32:
|
||||
; CHECK: v_add_f32_dpp {{v[0-9]+}}, {{v[0-9]+}}, v0 quad_perm:[3,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
|
||||
define amdgpu_kernel void @dpp_combine_f32(i32 addrspace(1)* %out, i32 %in) {
|
||||
%x = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
|
||||
%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 3, i32 1, i32 1, i1 1) #0
|
||||
%dpp.f32 = bitcast i32 %dpp to float
|
||||
%x.f32 = bitcast i32 %x to float
|
||||
%res.f32 = fadd float %x.f32, %dpp.f32
|
||||
%res = bitcast float %res.f32 to i32
|
||||
store i32 %res, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}dpp_combine_test_f32_mods:
|
||||
; CHECK: v_mul_f32_dpp {{v[0-9]+}}, |{{v[0-9]+}}|, -v0 quad_perm:[0,1,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
|
||||
define amdgpu_kernel void @dpp_combine_test_f32_mods(i32 addrspace(1)* %out, i32 %in) {
|
||||
%x = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
|
||||
%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 4, i32 1, i32 1, i1 1) #0
|
||||
|
||||
%x.f32 = bitcast i32 %x to float
|
||||
%x.f32.neg = fsub float -0.000000e+00, %x.f32
|
||||
|
||||
%dpp.f32 = bitcast i32 %dpp to float
|
||||
%dpp.f32.cmp = fcmp fast olt float %dpp.f32, 0.000000e+00
|
||||
%dpp.f32.sign = select i1 %dpp.f32.cmp, float -1.000000e+00, float 1.000000e+00
|
||||
%dpp.f32.abs = fmul fast float %dpp.f32, %dpp.f32.sign
|
||||
|
||||
%res.f32 = fmul float %x.f32.neg, %dpp.f32.abs
|
||||
%res = bitcast float %res.f32 to i32
|
||||
store i32 %res, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}dpp_combine_mac:
|
||||
; CHECK: v_mac_f32_dpp v0, {{v[0-9]+}}, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
|
||||
define amdgpu_kernel void @dpp_combine_mac(float addrspace(1)* %out, i32 %in) {
|
||||
%x = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%y = tail call i32 @llvm.amdgcn.workitem.id.y()
|
||||
%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 1, i32 1, i32 1, i1 1) #0
|
||||
%dpp.f32 = bitcast i32 %dpp to float
|
||||
%x.f32 = bitcast i32 %x to float
|
||||
%y.f32 = bitcast i32 %y to float
|
||||
|
||||
%mult = fmul float %dpp.f32, %y.f32
|
||||
%res = fadd float %mult, %x.f32
|
||||
store float %res, float addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}dpp_combine_sequence:
|
||||
define amdgpu_kernel void @dpp_combine_sequence(i32 addrspace(1)* %out, i32 %in, i1 %cmp) {
|
||||
%x = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 1, i32 1, i32 1, i1 1) #0
|
||||
br i1 %cmp, label %bb1, label %bb2
|
||||
bb1:
|
||||
; CHECK: v_add_u32_dpp {{v[0-9]+}}, vcc, {{v[0-9]+}}, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
|
||||
%resadd = add nsw i32 %dpp, %x
|
||||
br label %bb3
|
||||
bb2:
|
||||
; CHECK: v_subrev_u32_dpp {{v[0-9]+}}, vcc, {{v[0-9]+}}, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
|
||||
%ressub = sub nsw i32 %x, %dpp
|
||||
br label %bb3
|
||||
bb3:
|
||||
%res = phi i32 [%resadd, %bb1], [%ressub, %bb2]
|
||||
store i32 %res, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}dpp_combine_sequence_negative:
|
||||
; CHECK: v_mov_b32_dpp v1, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
|
||||
define amdgpu_kernel void @dpp_combine_sequence_negative(i32 addrspace(1)* %out, i32 %in, i1 %cmp) {
|
||||
%x = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 undef, i32 %in, i32 1, i32 1, i32 1, i1 1) #0
|
||||
br i1 %cmp, label %bb1, label %bb2
|
||||
bb1:
|
||||
%resadd = add nsw i32 %dpp, %x
|
||||
br label %bb3
|
||||
bb2:
|
||||
%ressub = sub nsw i32 2, %dpp ; break seq
|
||||
br label %bb3
|
||||
bb3:
|
||||
%res = phi i32 [%resadd, %bb1], [%ressub, %bb2]
|
||||
store i32 %res, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.amdgcn.workitem.id.x()
|
||||
declare i32 @llvm.amdgcn.workitem.id.y()
|
||||
declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #0
|
||||
|
||||
attributes #0 = { nounwind readnone convergent }
|
||||
|
|
@ -1,525 +0,0 @@
|
|||
# RUN: llc -march=amdgcn -mcpu=tonga -run-pass=gcn-dpp-combine -o - %s | FileCheck %s
|
||||
|
||||
---
|
||||
# old is undefined: only combine when masks are fully enabled and
|
||||
# bound_ctrl:0 is set, otherwise the result of DPP VALU op can be undefined.
|
||||
# CHECK-LABEL: name: old_is_undef
|
||||
# CHECK: %2:vgpr_32 = IMPLICIT_DEF
|
||||
# VOP2:
|
||||
# CHECK: %4:vgpr_32 = V_ADD_U32_dpp %2, %0, %1, 1, 15, 15, 1, implicit $exec
|
||||
# CHECK: %6:vgpr_32 = V_ADD_U32_e32 %5, %1, implicit $exec
|
||||
# CHECK: %8:vgpr_32 = V_ADD_U32_e32 %7, %1, implicit $exec
|
||||
# CHECK: %10:vgpr_32 = V_ADD_U32_e32 %9, %1, implicit $exec
|
||||
# VOP1:
|
||||
# CHECK: %12:vgpr_32 = V_NOT_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
|
||||
# CHECK: %14:vgpr_32 = V_NOT_B32_e32 %13, implicit $exec
|
||||
# CHECK: %16:vgpr_32 = V_NOT_B32_e32 %15, implicit $exec
|
||||
# CHECK: %18:vgpr_32 = V_NOT_B32_e32 %17, implicit $exec
|
||||
name: old_is_undef
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = IMPLICIT_DEF
|
||||
|
||||
; VOP2
|
||||
%3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
|
||||
%4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
|
||||
|
||||
%5:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec
|
||||
%6:vgpr_32 = V_ADD_U32_e32 %5, %1, implicit $exec
|
||||
|
||||
%7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec
|
||||
%8:vgpr_32 = V_ADD_U32_e32 %7, %1, implicit $exec
|
||||
|
||||
%9:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
|
||||
%10:vgpr_32 = V_ADD_U32_e32 %9, %1, implicit $exec
|
||||
|
||||
; VOP1
|
||||
%11:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
|
||||
%12:vgpr_32 = V_NOT_B32_e32 %11, implicit $exec
|
||||
|
||||
%13:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec
|
||||
%14:vgpr_32 = V_NOT_B32_e32 %13, implicit $exec
|
||||
|
||||
%15:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec
|
||||
%16:vgpr_32 = V_NOT_B32_e32 %15, implicit $exec
|
||||
|
||||
%17:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
|
||||
%18:vgpr_32 = V_NOT_B32_e32 %17, implicit $exec
|
||||
...
|
||||
|
||||
# old is the same as DPP src register: only combine when masks are fully enabled
|
||||
# othervise the result of DPP VALU can be undefined as its old is undef
|
||||
# CHECK-LABEL: name: old_is_same_as_src
|
||||
# VOP2:
|
||||
# CHECK: [[U1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
# CHECK: %3:vgpr_32 = V_ADD_U32_dpp [[U1]], %0, %1, 1, 15, 15, 1, implicit $exec
|
||||
# CHECK: [[U2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
# CHECK: %5:vgpr_32 = V_ADD_U32_dpp [[U2]], %0, %1, 1, 15, 15, 0, implicit $exec
|
||||
# CHECK: %7:vgpr_32 = V_ADD_U32_e32 %6, %1, implicit $exec
|
||||
# CHECK: %9:vgpr_32 = V_ADD_U32_e32 %8, %1, implicit $exec
|
||||
# VOP1:
|
||||
# CHECK: [[U3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
# CHECK: %11:vgpr_32 = V_NOT_B32_dpp [[U3]], %0, 1, 15, 15, 1, implicit $exec
|
||||
# CHECK: [[U4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
# CHECK: %13:vgpr_32 = V_NOT_B32_dpp [[U4]], %0, 1, 15, 15, 0, implicit $exec
|
||||
# CHECK: %15:vgpr_32 = V_NOT_B32_e32 %14, implicit $exec
|
||||
# CHECK: %17:vgpr_32 = V_NOT_B32_e32 %16, implicit $exec
|
||||
|
||||
name: old_is_same_as_src
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
|
||||
; VOP2
|
||||
%2:vgpr_32 = V_MOV_B32_dpp %0, %0, 1, 15, 15, 1, implicit $exec
|
||||
%3:vgpr_32 = V_ADD_U32_e32 %2, %1, implicit $exec
|
||||
|
||||
%4:vgpr_32 = V_MOV_B32_dpp %0, %0, 1, 15, 15, 0, implicit $exec
|
||||
%5:vgpr_32 = V_ADD_U32_e32 %4, %1, implicit $exec
|
||||
|
||||
%6:vgpr_32 = V_MOV_B32_dpp %0, %0, 1, 14, 15, 1, implicit $exec
|
||||
%7:vgpr_32 = V_ADD_U32_e32 %6, %1, implicit $exec
|
||||
|
||||
%8:vgpr_32 = V_MOV_B32_dpp %0, %0, 1, 14, 15, 0, implicit $exec
|
||||
%9:vgpr_32 = V_ADD_U32_e32 %8, %1, implicit $exec
|
||||
|
||||
; VOP1
|
||||
%10:vgpr_32 = V_MOV_B32_dpp %0, %0, 1, 15, 15, 1, implicit $exec
|
||||
%11:vgpr_32 = V_NOT_B32_e32 %10, implicit $exec
|
||||
|
||||
%12:vgpr_32 = V_MOV_B32_dpp %0, %0, 1, 15, 15, 0, implicit $exec
|
||||
%13:vgpr_32 = V_NOT_B32_e32 %12, implicit $exec
|
||||
|
||||
%14:vgpr_32 = V_MOV_B32_dpp %0, %0, 1, 14, 15, 1, implicit $exec
|
||||
%15:vgpr_32 = V_NOT_B32_e32 %14, implicit $exec
|
||||
|
||||
%16:vgpr_32 = V_MOV_B32_dpp %0, %0, 1, 14, 15, 0, implicit $exec
|
||||
%17:vgpr_32 = V_NOT_B32_e32 %16, implicit $exec
|
||||
...
|
||||
|
||||
# old is zero cases:
|
||||
|
||||
# CHECK-LABEL: name: old_is_0
|
||||
|
||||
# VOP2:
|
||||
# case 1: old is zero, masks are fully enabled, bound_ctrl:0 is on:
|
||||
# the DPP mov result would be either zero ({src lane disabled}|{src lane is
|
||||
# out of range}) or active src lane result - can combine with old = undef.
|
||||
# undef is preffered as it makes life easier for the regalloc.
|
||||
# CHECK: [[U1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
# CHECK: %4:vgpr_32 = V_ADD_U32_dpp [[U1]], %0, %1, 1, 15, 15, 1, implicit $exec
|
||||
|
||||
# case 2: old is zero, masks are fully enabled, bound_ctrl:0 is off:
|
||||
# as the DPP mov old is zero this case is no different from case 1 - combine it
|
||||
# setting bound_ctrl0 on for the combined DPP VALU op to make old undefined
|
||||
# CHECK: [[U2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
# CHECK: %6:vgpr_32 = V_ADD_U32_dpp [[U2]], %0, %1, 1, 15, 15, 1, implicit $exec
|
||||
|
||||
# case 3: masks are partialy disabled, bound_ctrl:0 is on:
|
||||
# the DPP mov result would be either zero ({src lane disabled}|{src lane is
|
||||
# out of range} or {the DPP mov's dest VGPR write is disabled by masks}) or
|
||||
# active src lane result - can combine with old = src1 of the VALU op.
|
||||
# The VALU op should have the same masks as DPP mov as they select lanes
|
||||
# with identity value.
|
||||
# Special case: the bound_ctrl for the combined DPP VALU op isn't important
|
||||
# here but let's make it off to keep the combiner's logic simpler.
|
||||
# CHECK: %8:vgpr_32 = V_ADD_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
|
||||
|
||||
# case 4: masks are partialy disabled, bound_ctrl:0 is off:
|
||||
# the DPP mov result would be either zero ({src lane disabled}|{src lane is
|
||||
# out of range} or {the DPP mov's dest VGPR write is disabled by masks}) or
|
||||
# active src lane result - can combine with old = src1 of the VALU op.
|
||||
# The VALU op should have the same masks as DPP mov as they select
|
||||
# lanes with identity value
|
||||
# CHECK: %10:vgpr_32 = V_ADD_U32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
|
||||
|
||||
# VOP1:
|
||||
# see case 1
|
||||
# CHECK: [[U3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
# CHECK: %12:vgpr_32 = V_NOT_B32_dpp [[U3]], %0, 1, 15, 15, 1, implicit $exec
|
||||
# see case 2
|
||||
# CHECK: [[U4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
# CHECK: %14:vgpr_32 = V_NOT_B32_dpp [[U4]], %0, 1, 15, 15, 1, implicit $exec
|
||||
# case 3 and 4 not appliable as there is no way to specify unchanged result
|
||||
# for the unary VALU op
|
||||
# CHECK: %16:vgpr_32 = V_NOT_B32_e32 %15, implicit $exec
|
||||
# CHECK: %18:vgpr_32 = V_NOT_B32_e32 %17, implicit $exec
|
||||
|
||||
name: old_is_0
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
|
||||
; VOP2
|
||||
%3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
|
||||
%4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
|
||||
|
||||
%5:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec
|
||||
%6:vgpr_32 = V_ADD_U32_e32 %5, %1, implicit $exec
|
||||
|
||||
%7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec
|
||||
%8:vgpr_32 = V_ADD_U32_e32 %7, %1, implicit $exec
|
||||
|
||||
%9:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
|
||||
%10:vgpr_32 = V_ADD_U32_e32 %9, %1, implicit $exec
|
||||
|
||||
; VOP1
|
||||
%11:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
|
||||
%12:vgpr_32 = V_NOT_B32_e32 %11, implicit $exec
|
||||
|
||||
%13:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec
|
||||
%14:vgpr_32 = V_NOT_B32_e32 %13, implicit $exec
|
||||
|
||||
%15:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec
|
||||
%16:vgpr_32 = V_NOT_B32_e32 %15, implicit $exec
|
||||
|
||||
%17:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
|
||||
%18:vgpr_32 = V_NOT_B32_e32 %17, implicit $exec
|
||||
...
|
||||
|
||||
# old is nonzero identity cases:
|
||||
|
||||
# old is nonzero identity, masks are fully enabled, bound_ctrl:0 is off:
|
||||
# the DPP mov result would be either identity ({src lane disabled}|{out of
|
||||
# range}) or src lane result - can combine with old = src1 of the VALU op
|
||||
# The DPP VALU op should have the same masks (and bctrl) as DPP mov as they
|
||||
# select lanes with identity value
|
||||
|
||||
# CHECK-LABEL: name: nonzero_old_is_identity_masks_enabled_bctl_off
|
||||
# CHECK: %4:vgpr_32 = V_MUL_U32_U24_dpp %1, %0, %1, 1, 15, 15, 0, implicit $exec
|
||||
# CHECK: %7:vgpr_32 = V_AND_B32_dpp %1, %0, %1, 1, 15, 15, 0, implicit $exec
|
||||
# CHECK: %10:vgpr_32 = V_MAX_I32_dpp %1, %0, %1, 1, 15, 15, 0, implicit $exec
|
||||
# CHECK: %13:vgpr_32 = V_MIN_I32_dpp %1, %0, %1, 1, 15, 15, 0, implicit $exec
|
||||
|
||||
name: nonzero_old_is_identity_masks_enabled_bctl_off
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
|
||||
%2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
|
||||
%3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 0, implicit $exec
|
||||
%4:vgpr_32 = V_MUL_U32_U24_e32 %3, %1, implicit $exec
|
||||
|
||||
%5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec
|
||||
%6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 15, 0, implicit $exec
|
||||
%7:vgpr_32 = V_AND_B32_e32 %6, %1, implicit $exec
|
||||
|
||||
%8:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
|
||||
%9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 15, 15, 0, implicit $exec
|
||||
%10:vgpr_32 = V_MAX_I32_e32 %9, %1, implicit $exec
|
||||
|
||||
%11:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec
|
||||
%12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 15, 0, implicit $exec
|
||||
%13:vgpr_32 = V_MIN_I32_e32 %12, %1, implicit $exec
|
||||
...
|
||||
|
||||
# old is nonzero identity, masks are partially enabled, bound_ctrl:0 is off:
|
||||
# the DPP mov result would be either identity ({src lane disabled}|{src lane is
|
||||
# out of range} or {the DPP mov's dest VGPR write is disabled by masks}) or
|
||||
# active src lane result - can combine with old = src1 of the VALU op.
|
||||
# The DPP VALU op should have the same masks (and bctrl) as DPP mov as they
|
||||
# select lanes with identity value
|
||||
|
||||
# CHECK-LABEL: name: nonzero_old_is_identity_masks_partially_disabled_bctl_off
|
||||
# CHECK: %4:vgpr_32 = V_MUL_U32_U24_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
|
||||
# CHECK: %7:vgpr_32 = V_AND_B32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec
|
||||
# CHECK: %10:vgpr_32 = V_MAX_I32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
|
||||
# CHECK: %13:vgpr_32 = V_MIN_I32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec
|
||||
|
||||
name: nonzero_old_is_identity_masks_partially_disabled_bctl_off
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
|
||||
%2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
|
||||
%3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
|
||||
%4:vgpr_32 = V_MUL_U32_U24_e32 %3, %1, implicit $exec
|
||||
|
||||
%5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec
|
||||
%6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 14, 0, implicit $exec
|
||||
%7:vgpr_32 = V_AND_B32_e32 %6, %1, implicit $exec
|
||||
|
||||
%8:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
|
||||
%9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 14, 15, 0, implicit $exec
|
||||
%10:vgpr_32 = V_MAX_I32_e32 %9, %1, implicit $exec
|
||||
|
||||
%11:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec
|
||||
%12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 14, 0, implicit $exec
|
||||
%13:vgpr_32 = V_MIN_I32_e32 %12, %1, implicit $exec
|
||||
...
|
||||
|
||||
# old is nonzero identity, masks are partially enabled, bound_ctrl:0 is on:
|
||||
# the DPP mov result may have 3 different values:
|
||||
# 1. the active src lane result
|
||||
# 2. 0 if the src lane is disabled|out of range
|
||||
# 3. DPP mov's old value if the mov's dest VGPR write is disabled by masks
|
||||
# can't combine
|
||||
|
||||
# CHECK-LABEL: name: nonzero_old_is_identity_masks_partially_disabled_bctl0
|
||||
# CHECK: %4:vgpr_32 = V_MUL_U32_U24_e32 %3, %1, implicit $exec
|
||||
# CHECK: %7:vgpr_32 = V_AND_B32_e32 %6, %1, implicit $exec
|
||||
# CHECK: %10:vgpr_32 = V_MAX_I32_e32 %9, %1, implicit $exec
|
||||
# CHECK: %13:vgpr_32 = V_MIN_I32_e32 %12, %1, implicit $exec
|
||||
|
||||
name: nonzero_old_is_identity_masks_partially_disabled_bctl0
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
|
||||
%2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
|
||||
%3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 1, implicit $exec
|
||||
%4:vgpr_32 = V_MUL_U32_U24_e32 %3, %1, implicit $exec
|
||||
|
||||
%5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec
|
||||
%6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 14, 1, implicit $exec
|
||||
%7:vgpr_32 = V_AND_B32_e32 %6, %1, implicit $exec
|
||||
|
||||
%8:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
|
||||
%9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 14, 15, 1, implicit $exec
|
||||
%10:vgpr_32 = V_MAX_I32_e32 %9, %1, implicit $exec
|
||||
|
||||
%11:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec
|
||||
%12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 14, 1, implicit $exec
|
||||
%13:vgpr_32 = V_MIN_I32_e32 %12, %1, implicit $exec
|
||||
...
|
||||
|
||||
# when the DPP source isn't a src0 operand the operation should be commuted if possible
|
||||
# CHECK-LABEL: name: dpp_commute
|
||||
# CHECK: %4:vgpr_32 = V_MUL_U32_U24_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
|
||||
# CHECK: %7:vgpr_32 = V_AND_B32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec
|
||||
# CHECK: %10:vgpr_32 = V_MAX_I32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
|
||||
# CHECK: %13:vgpr_32 = V_MIN_I32_dpp %1, %0, %1, 1, 15, 14, 0, implicit $exec
|
||||
# CHECK: %16:vgpr_32 = V_SUBREV_I32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec
|
||||
# CHECK: %19:vgpr_32 = V_ADD_I32_e32 5, %18, implicit-def $vcc, implicit $exec
|
||||
name: dpp_commute
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
|
||||
%2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
|
||||
%3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
|
||||
%4:vgpr_32 = V_MUL_U32_U24_e32 %1, %3, implicit $exec
|
||||
|
||||
%5:vgpr_32 = V_MOV_B32_e32 4294967295, implicit $exec
|
||||
%6:vgpr_32 = V_MOV_B32_dpp %5, %0, 1, 15, 14, 0, implicit $exec
|
||||
%7:vgpr_32 = V_AND_B32_e32 %1, %6, implicit $exec
|
||||
|
||||
%8:vgpr_32 = V_MOV_B32_e32 2147483647, implicit $exec
|
||||
%9:vgpr_32 = V_MOV_B32_dpp %8, %0, 1, 14, 15, 0, implicit $exec
|
||||
%10:vgpr_32 = V_MAX_I32_e32 %1, %9, implicit $exec
|
||||
|
||||
%11:vgpr_32 = V_MOV_B32_e32 -2147483648, implicit $exec
|
||||
%12:vgpr_32 = V_MOV_B32_dpp %11, %0, 1, 15, 14, 0, implicit $exec
|
||||
%13:vgpr_32 = V_MIN_I32_e32 %1, %12, implicit $exec
|
||||
|
||||
%14:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%15:vgpr_32 = V_MOV_B32_dpp %14, %0, 1, 14, 15, 0, implicit $exec
|
||||
%16:vgpr_32 = V_SUB_I32_e32 %1, %15, implicit-def $vcc, implicit $exec
|
||||
|
||||
; this cannot be combined because immediate as src0 isn't commutable
|
||||
%17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%18:vgpr_32 = V_MOV_B32_dpp %17, %0, 1, 14, 15, 0, implicit $exec
|
||||
%19:vgpr_32 = V_ADD_I32_e32 5, %18, implicit-def $vcc, implicit $exec
|
||||
...
|
||||
|
||||
# check for floating point modifiers
|
||||
# CHECK-LABEL: name: add_f32_e64
|
||||
# CHECK: %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
|
||||
# CHECK: %4:vgpr_32 = V_ADD_F32_e64 0, %3, 0, %0, 0, 1, implicit $exec
|
||||
# CHECK: %6:vgpr_32 = V_ADD_F32_dpp %2, 0, %1, 0, %0, 1, 15, 15, 1, implicit $exec
|
||||
# CHECK: %8:vgpr_32 = V_ADD_F32_dpp %2, 1, %1, 2, %0, 1, 15, 15, 1, implicit $exec
|
||||
# CHECK: %10:vgpr_32 = V_ADD_F32_e64 4, %9, 8, %0, 0, 0, implicit $exec
|
||||
|
||||
name: add_f32_e64
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = IMPLICIT_DEF
|
||||
|
||||
; this shouldn't be combined as omod is set
|
||||
%3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
|
||||
%4:vgpr_32 = V_ADD_F32_e64 0, %3, 0, %0, 0, 1, implicit $exec
|
||||
|
||||
; this should be combined as all modifiers are default
|
||||
%5:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
|
||||
%6:vgpr_32 = V_ADD_F32_e64 0, %5, 0, %0, 0, 0, implicit $exec
|
||||
|
||||
; this should be combined as modifiers other than abs|neg are default
|
||||
%7:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
|
||||
%8:vgpr_32 = V_ADD_F32_e64 1, %7, 2, %0, 0, 0, implicit $exec
|
||||
|
||||
; this shouldn't be combined as modifiers aren't abs|neg
|
||||
%9:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
|
||||
%10:vgpr_32 = V_ADD_F32_e64 4, %9, 8, %0, 0, 0, implicit $exec
|
||||
...
|
||||
|
||||
# tests on sequences of dpp consumers
|
||||
# CHECK-LABEL: name: dpp_seq
|
||||
# CHECK: %4:vgpr_32 = V_ADD_I32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec
|
||||
# CHECK: %5:vgpr_32 = V_SUBREV_I32_dpp %1, %0, %1, 1, 14, 15, 0, implicit-def $vcc, implicit $exec
|
||||
# CHECK: %6:vgpr_32 = V_OR_B32_dpp %1, %0, %1, 1, 14, 15, 0, implicit $exec
|
||||
# broken sequence:
|
||||
# CHECK: %7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
|
||||
|
||||
name: dpp_seq
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
|
||||
%3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
|
||||
%4:vgpr_32 = V_ADD_I32_e32 %3, %1, implicit-def $vcc, implicit $exec
|
||||
%5:vgpr_32 = V_SUB_I32_e32 %1, %3, implicit-def $vcc, implicit $exec
|
||||
%6:vgpr_32 = V_OR_B32_e32 %3, %1, implicit $exec
|
||||
|
||||
%7:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 14, 15, 0, implicit $exec
|
||||
%8:vgpr_32 = V_ADD_I32_e32 %7, %1, implicit-def $vcc, implicit $exec
|
||||
; this breaks the sequence
|
||||
%9:vgpr_32 = V_SUB_I32_e32 5, %7, implicit-def $vcc, implicit $exec
|
||||
...
|
||||
|
||||
# old reg def is in diff BB - cannot combine
|
||||
# CHECK-LABEL: name: old_in_diff_bb
|
||||
# CHECK: %3:vgpr_32 = V_MOV_B32_dpp %2, %1, 1, 1, 1, 0, implicit $exec
|
||||
|
||||
name: old_in_diff_bb
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
successors: %bb.1
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
S_BRANCH %bb.1
|
||||
|
||||
bb.1:
|
||||
%3:vgpr_32 = V_MOV_B32_dpp %2, %1, 1, 1, 1, 0, implicit $exec
|
||||
%4:vgpr_32 = V_ADD_U32_e32 %3, %0, implicit $exec
|
||||
...
|
||||
|
||||
# old reg def is in diff BB but bound_ctrl:0 - can combine
|
||||
# CHECK-LABEL: name: old_in_diff_bb_bctrl_zero
|
||||
# CHECK: %4:vgpr_32 = V_ADD_U32_dpp {{%[0-9]}}, %0, %1, 1, 15, 15, 1, implicit $exec
|
||||
|
||||
name: old_in_diff_bb_bctrl_zero
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
successors: %bb.1
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
S_BRANCH %bb.1
|
||||
|
||||
bb.1:
|
||||
%3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
|
||||
%4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
|
||||
...
|
||||
|
||||
# EXEC mask changed between def and use - cannot combine
|
||||
# CHECK-LABEL: name: exec_changed
|
||||
# CHECK: %3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
|
||||
|
||||
name: exec_changed
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%3:vgpr_32 = V_MOV_B32_dpp %2, %0, 1, 15, 15, 1, implicit $exec
|
||||
%4:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
|
||||
%5:sreg_64 = COPY $exec, implicit-def $exec
|
||||
%6:vgpr_32 = V_ADD_U32_e32 %3, %1, implicit $exec
|
||||
...
|
||||
|
||||
# test if $old definition is correctly tracked through subreg manipulation pseudos
|
||||
|
||||
# CHECK-LABEL: name: mul_old_subreg
|
||||
# CHECK: %7:vgpr_32 = V_MUL_I32_I24_dpp %0.sub1, %1, %0.sub1, 1, 1, 1, 0, implicit $exec
|
||||
|
||||
name: mul_old_subreg
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
%0:vreg_64 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
|
||||
%3:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
|
||||
%4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
|
||||
%5:vreg_64 = INSERT_SUBREG %4, %1, %subreg.sub1 ; %5.sub0 is taken from %4
|
||||
%6:vgpr_32 = V_MOV_B32_dpp %5.sub0, %1, 1, 1, 1, 0, implicit $exec
|
||||
%7:vgpr_32 = V_MUL_I32_I24_e32 %6, %0.sub1, implicit $exec
|
||||
...
|
||||
|
||||
# CHECK-LABEL: name: add_old_subreg
|
||||
# CHECK: %5:vgpr_32 = V_ADD_U32_dpp %0.sub1, %1, %0.sub1, 1, 1, 1, 0, implicit $exec
|
||||
|
||||
name: add_old_subreg
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
%0:vreg_64 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%3:vreg_64 = INSERT_SUBREG %0, %2, %subreg.sub1 ; %3.sub1 is inserted
|
||||
%4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 1, 1, 0, implicit $exec
|
||||
%5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec
|
||||
...
|
||||
|
||||
# CHECK-LABEL: name: add_old_subreg_undef
|
||||
# CHECK: %5:vgpr_32 = V_ADD_U32_dpp %3.sub1, %1, %0.sub1, 1, 15, 15, 1, implicit $exec
|
||||
|
||||
name: add_old_subreg_undef
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
%0:vreg_64 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%3:vreg_64 = REG_SEQUENCE %2, %subreg.sub0 ; %3.sub1 is undef
|
||||
%4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 15, 15, 1, implicit $exec
|
||||
%5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
# RUN: llc -march=amdgcn -mcpu=tonga -run-pass=gcn-dpp-combine -o - %s | FileCheck %s
|
||||
|
||||
# test if $old definition is correctly tracked through subreg manipulation pseudos
|
||||
|
||||
---
|
||||
# CHECK-LABEL: name: mul_old_subreg
|
||||
# CHECK: %7:vgpr_32 = V_MUL_I32_I24_dpp %0.sub1, %1, %0.sub1, 1, 1, 1, 0, implicit $exec
|
||||
|
||||
name: mul_old_subreg
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: vgpr_32 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
- { id: 3, class: vgpr_32 }
|
||||
- { id: 4, class: vreg_64 }
|
||||
- { id: 5, class: vreg_64 }
|
||||
- { id: 6, class: vgpr_32 }
|
||||
- { id: 7, class: vgpr_32 }
|
||||
|
||||
liveins:
|
||||
- { reg: '$vgpr0', virtual-reg: '%0' }
|
||||
- { reg: '$vgpr1', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
%0:vreg_64 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
|
||||
%3:vgpr_32 = V_MOV_B32_e32 42, implicit $exec
|
||||
%4 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
|
||||
%5 = INSERT_SUBREG %4, %1, %subreg.sub1 ; %5.sub0 is taken from %4
|
||||
%6:vgpr_32 = V_MOV_B32_dpp %5.sub0, %1, 1, 1, 1, 0, implicit $exec
|
||||
%7:vgpr_32 = V_MUL_I32_I24_e32 %6, %0.sub1, implicit $exec
|
||||
...
|
||||
|
||||
# CHECK-LABEL: name: add_old_subreg
|
||||
# CHECK: [[OLD:\%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
# CHECK: %5:vgpr_32 = V_ADD_U32_dpp [[OLD]], %1, %0.sub1, 1, 1, 1, 1, implicit $exec
|
||||
|
||||
name: add_old_subreg
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: vgpr_32 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
- { id: 3, class: vreg_64 }
|
||||
- { id: 4, class: vgpr_32 }
|
||||
- { id: 5, class: vgpr_32 }
|
||||
|
||||
liveins:
|
||||
- { reg: '$vgpr0', virtual-reg: '%0' }
|
||||
- { reg: '$vgpr1', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
%0:vreg_64 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%3:vreg_64 = INSERT_SUBREG %0, %2, %subreg.sub1 ; %3.sub1 is inserted
|
||||
%4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 1, 1, 0, implicit $exec
|
||||
%5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec
|
||||
...
|
||||
|
||||
# CHECK-LABEL: name: add_old_subreg_undef
|
||||
# CHECK: %5:vgpr_32 = V_ADD_U32_dpp %3.sub1, %1, %0.sub1, 1, 1, 1, 0, implicit $exec
|
||||
|
||||
name: add_old_subreg_undef
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: vgpr_32 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
- { id: 3, class: vreg_64 }
|
||||
- { id: 4, class: vgpr_32 }
|
||||
- { id: 5, class: vgpr_32 }
|
||||
|
||||
liveins:
|
||||
- { reg: '$vgpr0', virtual-reg: '%0' }
|
||||
- { reg: '$vgpr1', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
%0:vreg_64 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%3:vreg_64 = REG_SEQUENCE %2, %subreg.sub0 ; %3.sub1 is undef
|
||||
%4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 1, 1, 0, implicit $exec
|
||||
%5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec
|
||||
...
|
||||
|
||||
# CHECK-LABEL: name: add_f32_e64
|
||||
# CHECK: %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 1, 1, 1, implicit $exec
|
||||
# CHECK: %4:vgpr_32 = V_ADD_F32_e64 0, %3, 0, %0, 0, 1, implicit $exec
|
||||
# CHECK: %6:vgpr_32 = V_ADD_F32_dpp %2, 0, %1, 0, %0, 1, 1, 1, 1, implicit $exec
|
||||
# CHECK: %7:vgpr_32 = V_ADD_F32_dpp %2, 1, %1, 2, %0, 1, 1, 1, 1, implicit $exec
|
||||
# CHECK: %9:vgpr_32 = V_ADD_F32_e64 4, %8, 8, %0, 0, 0, implicit $exec
|
||||
|
||||
name: add_f32_e64
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vgpr_32 }
|
||||
- { id: 1, class: vgpr_32 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
- { id: 3, class: vgpr_32 }
|
||||
- { id: 4, class: vgpr_32 }
|
||||
- { id: 5, class: vgpr_32 }
|
||||
- { id: 6, class: vgpr_32 }
|
||||
- { id: 7, class: vgpr_32 }
|
||||
- { id: 8, class: vgpr_32 }
|
||||
- { id: 9, class: vgpr_32 }
|
||||
|
||||
liveins:
|
||||
- { reg: '$vgpr0', virtual-reg: '%0' }
|
||||
- { reg: '$vgpr1', virtual-reg: '%1' }
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
%0:vgpr_32 = COPY $vgpr0
|
||||
%1:vgpr_32 = COPY $vgpr1
|
||||
%2:vgpr_32 = IMPLICIT_DEF
|
||||
%3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 1, 1, 1, implicit $exec
|
||||
|
||||
; this shouldn't be combined as omod is set
|
||||
%4:vgpr_32 = V_ADD_F32_e64 0, %3, 0, %0, 0, 1, implicit $exec
|
||||
|
||||
%5:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 1, 1, 1, implicit $exec
|
||||
|
||||
; this should be combined as all modifiers are default
|
||||
%6:vgpr_32 = V_ADD_F32_e64 0, %5, 0, %0, 0, 0, implicit $exec
|
||||
|
||||
; this should be combined as modifiers other than abs|neg are default
|
||||
%7:vgpr_32 = V_ADD_F32_e64 1, %5, 2, %0, 0, 0, implicit $exec
|
||||
|
||||
%8:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 1, 1, 1, implicit $exec
|
||||
|
||||
; this shouldn't be combined as modifiers aren't abs|neg
|
||||
%9:vgpr_32 = V_ADD_F32_e64 4, %8, 8, %0, 0, 0, implicit $exec
|
||||
...
|
||||
Loading…
Reference in New Issue