forked from OSchip/llvm-project
[X86] Use intrinsics table for PMADDUBSW and PMADDWD so that we can use the legacy intrinsics to select EVEX encoded instructions when available.
This removes a couple tablegen classes that become unused after this change. Another class gained an additional parameter to allow PMADDUBSW to specify a different result type from its input type. llvm-svn: 285515
This commit is contained in:
Craig Topper
parent
72f9ed1807
commit
b7781a95fd
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@ -1099,7 +1099,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::PINSRDrr, X86::PINSRDrm, 0 },
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{ X86::PINSRQrr, X86::PINSRQrm, 0 },
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{ X86::PINSRWrri, X86::PINSRWrmi, 0 },
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{ X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
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{ X86::PMADDUBSWrr, X86::PMADDUBSWrm, TB_ALIGN_16 },
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{ X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
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{ X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
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{ X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
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@ -1397,7 +1397,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::VPINSRDrr, X86::VPINSRDrm, 0 },
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{ X86::VPINSRQrr, X86::VPINSRQrm, 0 },
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{ X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
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{ X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
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{ X86::VPMADDUBSWrr, X86::VPMADDUBSWrm, 0 },
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{ X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
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{ X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
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{ X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
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@ -1557,7 +1557,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
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{ X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
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{ X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
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{ X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
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{ X86::VPMADDUBSWYrr, X86::VPMADDUBSWYrm, 0 },
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{ X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
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{ X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
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{ X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
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@ -3970,47 +3970,6 @@ def SSE_PMADD : OpndItins<
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let ExeDomain = SSEPackedInt in { // SSE integer instructions
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multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
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RegisterClass RC, PatFrag memop_frag,
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X86MemOperand x86memop,
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OpndItins itins,
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bit IsCommutable = 0,
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bit Is2Addr = 1> {
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let isCommutable = IsCommutable in
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def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
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Sched<[itins.Sched]>;
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def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
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itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
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Intrinsic IntId256, OpndItins itins,
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bit IsCommutable = 0> {
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let Predicates = [HasAVX] in
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defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
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VR128, loadv2i64, i128mem, itins,
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IsCommutable, 0>, VEX_4V;
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let Constraints = "$src1 = $dst" in
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defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
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i128mem, itins, IsCommutable, 1>;
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let Predicates = [HasAVX2] in
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defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
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VR256, loadv4i64, i256mem, itins,
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IsCommutable, 0>, VEX_4V, VEX_L;
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}
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/// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
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multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType DstVT, ValueType SrcVT, RegisterClass RC,
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@ -4086,9 +4045,17 @@ defm PAVGB : PDI_binop_all<0xE0, "pavgb", X86avg, v16i8, v32i8,
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defm PAVGW : PDI_binop_all<0xE3, "pavgw", X86avg, v8i16, v16i16,
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SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
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// Intrinsic forms
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defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
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int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
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let Predicates = [HasAVX, NoVLX_Or_NoBWI] in
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defm VPMADDWD : PDI_binop_rm2<0xF5, "vpmaddwd", X86vpmaddwd, v4i32, v8i16, VR128,
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loadv2i64, i128mem, SSE_PMADD, 0>, VEX_4V;
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let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in
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defm VPMADDWDY : PDI_binop_rm2<0xF5, "vpmaddwd", X86vpmaddwd, v8i32, v16i16,
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VR256, loadv4i64, i128mem, SSE_PMADD,
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0>, VEX_4V, VEX_L;
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let Constraints = "$src1 = $dst" in
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defm PMADDWD : PDI_binop_rm2<0xF5, "pmaddwd", X86vpmaddwd, v4i32, v8i16, VR128,
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memopv2i64, i128mem, SSE_PMADD>;
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let Predicates = [HasAVX, NoVLX_Or_NoBWI] in
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defm VPSADBW : PDI_binop_rm2<0xF6, "vpsadbw", X86psadbw, v2i64, v16i8, VR128,
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@ -5529,16 +5496,16 @@ def SSE_PMULHRSW : OpndItins<
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/// SS3I_binop_rm - Simple SSSE3 bin op
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multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
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X86MemOperand x86memop, OpndItins itins,
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bit Is2Addr = 1> {
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ValueType DstVT, ValueType OpVT, RegisterClass RC,
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PatFrag memop_frag, X86MemOperand x86memop,
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OpndItins itins, bit Is2Addr = 1> {
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let isCommutable = 1 in
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def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
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[(set RC:$dst, (DstVT (OpNode (OpVT RC:$src1), RC:$src2)))], itins.rr>,
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Sched<[itins.Sched]>;
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def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, x86memop:$src2),
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@ -5546,7 +5513,7 @@ multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set RC:$dst,
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(OpVT (OpNode RC:$src1,
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(DstVT (OpNode (OpVT RC:$src1),
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(bitconvert (memop_frag addr:$src2)))))], itins.rm>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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@ -5593,27 +5560,30 @@ multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
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let ImmT = NoImm, Predicates = [HasAVX, NoVLX_Or_NoBWI] in {
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let isCommutable = 0 in {
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defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
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loadv2i64, i128mem,
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defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, v16i8,
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VR128, loadv2i64, i128mem,
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SSE_PSHUFB, 0>, VEX_4V;
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}
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defm VPMULHRSW : SS3I_binop_rm<0x0B, "vpmulhrsw", X86mulhrs, v8i16, VR128,
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loadv2i64, i128mem,
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defm VPMULHRSW : SS3I_binop_rm<0x0B, "vpmulhrsw", X86mulhrs, v8i16, v8i16,
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VR128, loadv2i64, i128mem,
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SSE_PMULHRSW, 0>, VEX_4V;
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defm VPMADDUBSW : SS3I_binop_rm<0x04, "vpmaddubsw", X86vpmaddubsw, v8i16,
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v16i8, VR128, loadv2i64, i128mem,
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SSE_PMADD, 0>, VEX_4V;
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}
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let ImmT = NoImm, Predicates = [HasAVX] in {
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let isCommutable = 0 in {
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defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
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defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, v8i16, VR128,
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loadv2i64, i128mem,
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SSE_PHADDSUBW, 0>, VEX_4V;
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defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
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defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, v4i32, VR128,
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loadv2i64, i128mem,
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SSE_PHADDSUBD, 0>, VEX_4V;
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defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
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defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, v8i16, VR128,
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loadv2i64, i128mem,
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SSE_PHADDSUBW, 0>, VEX_4V;
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defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
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defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, v4i32, VR128,
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loadv2i64, i128mem,
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SSE_PHADDSUBD, 0>, VEX_4V;
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defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb",
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@ -5631,35 +5601,35 @@ let isCommutable = 0 in {
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defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
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int_x86_ssse3_phsub_sw_128,
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SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
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defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
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int_x86_ssse3_pmadd_ub_sw_128,
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SSE_PMADD, loadv2i64, 0>, VEX_4V;
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}
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}
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let ImmT = NoImm, Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
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let isCommutable = 0 in {
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defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
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loadv4i64, i256mem,
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defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, v32i8,
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VR256, loadv4i64, i256mem,
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SSE_PSHUFB, 0>, VEX_4V, VEX_L;
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}
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defm VPMULHRSWY : SS3I_binop_rm<0x0B, "vpmulhrsw", X86mulhrs, v16i16, VR256,
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loadv4i64, i256mem,
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defm VPMULHRSWY : SS3I_binop_rm<0x0B, "vpmulhrsw", X86mulhrs, v16i16, v16i16,
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VR256, loadv4i64, i256mem,
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SSE_PMULHRSW, 0>, VEX_4V, VEX_L;
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defm VPMADDUBSWY : SS3I_binop_rm<0x04, "vpmaddubsw", X86vpmaddubsw, v16i16,
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v32i8, VR256, loadv4i64, i256mem,
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SSE_PMADD, 0>, VEX_4V, VEX_L;
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}
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let ImmT = NoImm, Predicates = [HasAVX2] in {
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let isCommutable = 0 in {
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defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
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defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, v16i16,
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VR256, loadv4i64, i256mem,
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SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
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defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, v8i32, VR256,
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loadv4i64, i256mem,
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SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
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defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
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loadv4i64, i256mem,
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defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, v16i16,
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VR256, loadv4i64, i256mem,
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SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
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defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
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loadv4i64, i256mem,
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SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
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defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
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defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, v8i32, VR256,
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loadv4i64, i256mem,
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SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
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defm VPSIGNBY : SS3I_binop_rm_int_y<0x08, "vpsignb", int_x86_avx2_psign_b,
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@ -5674,22 +5644,19 @@ let isCommutable = 0 in {
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defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
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int_x86_avx2_phsub_sw,
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WriteVecALU>, VEX_4V, VEX_L;
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defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
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int_x86_avx2_pmadd_ub_sw,
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WriteVecIMul>, VEX_4V, VEX_L;
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}
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}
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// None of these have i8 immediate fields.
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let ImmT = NoImm, Constraints = "$src1 = $dst" in {
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let isCommutable = 0 in {
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defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
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defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, v8i16, VR128,
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memopv2i64, i128mem, SSE_PHADDSUBW>;
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defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
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defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, v4i32, VR128,
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memopv2i64, i128mem, SSE_PHADDSUBD>;
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defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
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defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, v8i16, VR128,
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memopv2i64, i128mem, SSE_PHADDSUBW>;
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defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
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defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, v4i32, VR128,
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memopv2i64, i128mem, SSE_PHADDSUBD>;
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defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", int_x86_ssse3_psign_b_128,
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SSE_PSIGN, memopv2i64>;
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@ -5697,7 +5664,7 @@ let isCommutable = 0 in {
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SSE_PSIGN, memopv2i64>;
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defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", int_x86_ssse3_psign_d_128,
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SSE_PSIGN, memopv2i64>;
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defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
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defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, v16i8, VR128,
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memopv2i64, i128mem, SSE_PSHUFB>;
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defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
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int_x86_ssse3_phadd_sw_128,
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@ -5705,12 +5672,12 @@ let isCommutable = 0 in {
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defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
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int_x86_ssse3_phsub_sw_128,
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SSE_PHADDSUBSW, memopv2i64>;
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defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
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int_x86_ssse3_pmadd_ub_sw_128,
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SSE_PMADD, memopv2i64>;
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defm PMADDUBSW : SS3I_binop_rm<0x04, "pmaddubsw", X86vpmaddubsw, v8i16,
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v16i8, VR128, memopv2i64, i128mem,
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SSE_PMADD>;
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}
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defm PMULHRSW : SS3I_binop_rm<0x0B, "pmulhrsw", X86mulhrs, v8i16, VR128,
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memopv2i64, i128mem, SSE_PMULHRSW>;
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defm PMULHRSW : SS3I_binop_rm<0x0B, "pmulhrsw", X86mulhrs, v8i16, v8i16,
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VR128, memopv2i64, i128mem, SSE_PMULHRSW>;
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}
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||||
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//===---------------------------------------------------------------------===//
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@ -289,6 +289,8 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx2_phadd_w, INTR_TYPE_2OP, X86ISD::HADD, 0),
|
||||
X86_INTRINSIC_DATA(avx2_phsub_d, INTR_TYPE_2OP, X86ISD::HSUB, 0),
|
||||
X86_INTRINSIC_DATA(avx2_phsub_w, INTR_TYPE_2OP, X86ISD::HSUB, 0),
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||||
X86_INTRINSIC_DATA(avx2_pmadd_ub_sw, INTR_TYPE_2OP, X86ISD::VPMADDUBSW, 0),
|
||||
X86_INTRINSIC_DATA(avx2_pmadd_wd, INTR_TYPE_2OP, X86ISD::VPMADDWD, 0),
|
||||
X86_INTRINSIC_DATA(avx2_pmovmskb, INTR_TYPE_1OP, X86ISD::MOVMSK, 0),
|
||||
X86_INTRINSIC_DATA(avx2_pmul_dq, INTR_TYPE_2OP, X86ISD::PMULDQ, 0),
|
||||
X86_INTRINSIC_DATA(avx2_pmul_hr_sw, INTR_TYPE_2OP, X86ISD::MULHRS, 0),
|
||||
|
|
@ -1760,6 +1762,7 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
|||
X86_INTRINSIC_DATA(sse2_paddus_w, INTR_TYPE_2OP, X86ISD::ADDUS, 0),
|
||||
X86_INTRINSIC_DATA(sse2_pavg_b, INTR_TYPE_2OP, X86ISD::AVG, 0),
|
||||
X86_INTRINSIC_DATA(sse2_pavg_w, INTR_TYPE_2OP, X86ISD::AVG, 0),
|
||||
X86_INTRINSIC_DATA(sse2_pmadd_wd, INTR_TYPE_2OP, X86ISD::VPMADDWD, 0),
|
||||
X86_INTRINSIC_DATA(sse2_pmovmskb_128, INTR_TYPE_1OP, X86ISD::MOVMSK, 0),
|
||||
X86_INTRINSIC_DATA(sse2_pmulh_w, INTR_TYPE_2OP, ISD::MULHS, 0),
|
||||
X86_INTRINSIC_DATA(sse2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
|
||||
|
|
@ -1808,6 +1811,7 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
|||
X86_INTRINSIC_DATA(ssse3_phadd_w_128, INTR_TYPE_2OP, X86ISD::HADD, 0),
|
||||
X86_INTRINSIC_DATA(ssse3_phsub_d_128, INTR_TYPE_2OP, X86ISD::HSUB, 0),
|
||||
X86_INTRINSIC_DATA(ssse3_phsub_w_128, INTR_TYPE_2OP, X86ISD::HSUB, 0),
|
||||
X86_INTRINSIC_DATA(ssse3_pmadd_ub_sw_128, INTR_TYPE_2OP, X86ISD::VPMADDUBSW, 0),
|
||||
X86_INTRINSIC_DATA(ssse3_pmul_hr_sw_128, INTR_TYPE_2OP, X86ISD::MULHRS, 0),
|
||||
X86_INTRINSIC_DATA(ssse3_pshuf_b_128, INTR_TYPE_2OP, X86ISD::PSHUFB, 0),
|
||||
X86_INTRINSIC_DATA(xop_vpcomb, INTR_TYPE_3OP, X86ISD::VPCOM, 0),
|
||||
|
|
|
|||
Loading…
Reference in New Issue