forked from OSchip/llvm-project
[MachineScheduler] Reduce reordering due to mem op clustering
Summary: Mem op clustering adds a weak edge in the DAG between two loads or stores that should be clustered, but the direction of this edge is pretty arbitrary (it depends on the sort order of MemOpInfo, which represents the operands of a load or store). This often means that two loads or stores will get reordered even if they would naturally have been scheduled together anyway, which leads to test case churn and goes against the scheduler's "do no harm" philosophy. The fix makes sure that the direction of the edge always matches the original code order of the instructions. Reviewers: atrick, MatzeB, arsenm, rampitec, t.p.northover Subscribers: jvesely, wdng, nhaehnle, kristof.beyls, hiraditya, javed.absar, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72706
This commit is contained in:
Jay Foad
parent
ab72db7fc8
commit
b777e551f0
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@ -1573,6 +1573,8 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps(
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for (unsigned Idx = 0, End = MemOpRecords.size(); Idx < (End - 1); ++Idx) {
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SUnit *SUa = MemOpRecords[Idx].SU;
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SUnit *SUb = MemOpRecords[Idx+1].SU;
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if (SUa->NodeNum > SUb->NodeNum)
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std::swap(SUa, SUb);
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if (TII->shouldClusterMemOps(*MemOpRecords[Idx].BaseOp,
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*MemOpRecords[Idx + 1].BaseOp,
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ClusterLength) &&
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@ -3,7 +3,7 @@
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: stp_i64_scale:%bb.0
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; CHECK:Cluster ld/st SU(4) - SU(3)
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; CHECK:Cluster ld/st SU(3) - SU(4)
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; CHECK:Cluster ld/st SU(2) - SU(5)
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; CHECK:SU(4): STRXui %1:gpr64, %0:gpr64common, 1
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; CHECK:SU(3): STRXui %1:gpr64, %0:gpr64common, 2
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@ -24,7 +24,7 @@ entry:
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: stp_i32_scale:%bb.0
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; CHECK:Cluster ld/st SU(4) - SU(3)
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; CHECK:Cluster ld/st SU(3) - SU(4)
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; CHECK:Cluster ld/st SU(2) - SU(5)
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; CHECK:SU(4): STRWui %1:gpr32, %0:gpr64common, 1
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; CHECK:SU(3): STRWui %1:gpr32, %0:gpr64common, 2
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@ -45,12 +45,12 @@ entry:
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; CHECK:********** MI Scheduling **********
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; CHECK-LABEL:stp_i64_unscale:%bb.0 entry
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; CHECK:Cluster ld/st SU(5) - SU(2)
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; CHECK:Cluster ld/st SU(4) - SU(3)
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; CHECK:SU(5): STURXi %1:gpr64, %0:gpr64common, -32
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; CHECK:Cluster ld/st SU(2) - SU(5)
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; CHECK:Cluster ld/st SU(3) - SU(4)
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; CHECK:SU(2): STURXi %1:gpr64, %0:gpr64common, -24
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; CHECK:SU(4): STURXi %1:gpr64, %0:gpr64common, -16
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; CHECK:SU(3): STURXi %1:gpr64, %0:gpr64common, -8
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; CHECK:SU(4): STURXi %1:gpr64, %0:gpr64common, -16
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; CHECK:SU(5): STURXi %1:gpr64, %0:gpr64common, -32
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define void @stp_i64_unscale(i64* nocapture %P, i64 %v) #0 {
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entry:
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%arrayidx = getelementptr inbounds i64, i64* %P, i64 -3
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@ -66,12 +66,12 @@ entry:
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; CHECK:********** MI Scheduling **********
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; CHECK-LABEL:stp_i32_unscale:%bb.0 entry
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; CHECK:Cluster ld/st SU(5) - SU(2)
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; CHECK:Cluster ld/st SU(4) - SU(3)
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; CHECK:SU(5): STURWi %1:gpr32, %0:gpr64common, -16
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; CHECK:Cluster ld/st SU(2) - SU(5)
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; CHECK:Cluster ld/st SU(3) - SU(4)
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; CHECK:SU(2): STURWi %1:gpr32, %0:gpr64common, -12
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; CHECK:SU(4): STURWi %1:gpr32, %0:gpr64common, -8
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; CHECK:SU(3): STURWi %1:gpr32, %0:gpr64common, -4
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; CHECK:SU(4): STURWi %1:gpr32, %0:gpr64common, -8
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; CHECK:SU(5): STURWi %1:gpr32, %0:gpr64common, -16
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define void @stp_i32_unscale(i32* nocapture %P, i32 %v) #0 {
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entry:
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%arrayidx = getelementptr inbounds i32, i32* %P, i32 -3
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@ -36,7 +36,7 @@ define i64 @ldp_sext_int(i32* %p) nounwind {
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; Test ldur clustering.
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: ldur_int:%bb.0
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; CHECK: Cluster ld/st SU(2) - SU(1)
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; CHECK: Cluster ld/st SU(1) - SU(2)
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; CHECK: SU(1): %{{[0-9]+}}:gpr32 = LDURWi
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; CHECK: SU(2): %{{[0-9]+}}:gpr32 = LDURWi
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define i32 @ldur_int(i32* %a) nounwind {
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@ -259,9 +259,9 @@ define void @memset_12_stack() {
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define void @memset_16_stack() {
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; CHECK-LABEL: memset_16_stack:
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; CHECK: mov x8, #-6148914691236517206
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; CHECK-NEXT: str x8, [sp, #-32]!
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; CHECK-NEXT: mov x0, sp
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; CHECK-NEXT: stp x8, x30, [sp, #8]
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; CHECK-NEXT: str x8, [sp]
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; CHECK-NEXT: bl something
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%buf = alloca [16 x i8], align 1
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%cast = bitcast [16 x i8]* %buf to i8*
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@ -6,17 +6,17 @@ define void @foo(i32 %In1, <2 x i128> %In2, <2 x i128> %In3, <2 x i128> *%Out) {
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0x1
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; CHECK-NEXT: fmov s0, wzr
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; CHECK-NEXT: ldp x10, x9, [sp, #8]
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; CHECK-NEXT: fmov s1, w8
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; CHECK-NEXT: ldr x8, [sp]
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; CHECK-NEXT: ldp x8, x9, [sp, #8]
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; CHECK-NEXT: ldr x10, [sp]
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; CHECK-NEXT: cmeq v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: fmov w11, s0
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; CHECK-NEXT: tst w11, #0x1
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; CHECK-NEXT: csel x11, x2, x6, ne
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; CHECK-NEXT: csel x12, x3, x7, ne
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; CHECK-NEXT: csel x8, x4, x8, ne
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; CHECK-NEXT: csel x10, x5, x10, ne
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; CHECK-NEXT: stp x8, x10, [x9, #16]
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; CHECK-NEXT: csel x10, x4, x10, ne
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; CHECK-NEXT: csel x8, x5, x8, ne
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; CHECK-NEXT: stp x10, x8, [x9, #16]
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; CHECK-NEXT: stp x11, x12, [x9]
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; CHECK-NEXT: ret
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%cond = and i32 %In1, 1
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@ -65,8 +65,8 @@ define void @f3(i32 %a1, i32 %a2) #0 {
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define void @f4(i32 %a1, i32 %a2, i32 %a3) #0 {
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; CHECK-NEXT: adrp x8, [[SET3]]@PAGE
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; CHECK-NEXT: add x8, x8, [[SET3]]@PAGEOFF
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; CHECK-NEXT: stp w2, w0, [x8]
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; CHECK-NEXT: str w1, [x8, #8]
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; CHECK-NEXT: stp w0, w1, [x8, #4]
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; CHECK-NEXT: str w2, [x8]
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; CHECK-NEXT: ret
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store i32 %a1, i32* @m4, align 4
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store i32 %a2, i32* @n4, align 4
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@ -18,8 +18,8 @@
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---
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# CHECK-LABEL: name: load_imp-def
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# CHECK: bb.0.entry:
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# CHECK: LDRWui $x0, 0
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# CHECK: LDRWui $x0, 1
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# CHECK: LDRWui $x0, 0
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# CHECK: STRWui $w1, $x0, 2
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name: load_imp-def
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tracksRegLiveness: true
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@ -1,9 +1,9 @@
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}cast_constant_i64_to_build_vector_v4i16:
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; GCN: global_store_dwordx2
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; GCN: global_store_dword v
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; GCN: global_store_short
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; GCN: global_store_dword v
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; GCN: global_store_dwordx2
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define amdgpu_kernel void @cast_constant_i64_to_build_vector_v4i16(i8 addrspace(1)* nocapture %data) {
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entry:
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store i8 72, i8 addrspace(1)* %data, align 1
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@ -133,10 +133,10 @@ entry:
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; GCN-DAG: buffer_store_dword [[LOAD2]], off, s[0:3], s32 offset:8
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; GCN-DAG: buffer_store_dword [[LOAD3]], off, s[0:3], s32 offset:12
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; GCN: buffer_load_dword [[LOAD4:v[0-9]+]], off, s[0:3], s34 offset:16
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; GCN: buffer_load_dword [[LOAD5:v[0-9]+]], off, s[0:3], s34 offset:20
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; GCN: buffer_load_dword [[LOAD6:v[0-9]+]], off, s[0:3], s34 offset:24
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; GCN: buffer_load_dword [[LOAD7:v[0-9]+]], off, s[0:3], s34 offset:28
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; GCN: buffer_load_dword [[LOAD4:v[0-9]+]], off, s[0:3], s34 offset:16
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; GCN-DAG: buffer_store_dword [[LOAD4]], off, s[0:3], s32 offset:16
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; GCN-DAG: buffer_store_dword [[LOAD5]], off, s[0:3], s32 offset:20
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@ -331,10 +331,10 @@ entry:
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; GCN-DAG: buffer_store_dword [[LOAD2]], off, s[0:3], s32 offset:8
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; GCN-DAG: buffer_store_dword [[LOAD3]], off, s[0:3], s32 offset:12
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; GCN: buffer_load_dword [[LOAD4:v[0-9]+]], off, s[0:3], s34 offset:16
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; GCN: buffer_load_dword [[LOAD5:v[0-9]+]], off, s[0:3], s34 offset:20
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; GCN: buffer_load_dword [[LOAD6:v[0-9]+]], off, s[0:3], s34 offset:24
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; GCN: buffer_load_dword [[LOAD7:v[0-9]+]], off, s[0:3], s34 offset:28
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; GCN: buffer_load_dword [[LOAD4:v[0-9]+]], off, s[0:3], s34 offset:16
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; GCN: s_waitcnt vmcnt(0)
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; GCN-DAG: buffer_store_dword [[LOAD4]], off, s[0:3], s32 offset:16
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@ -765,16 +765,17 @@ entry:
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; GCN-LABEL: {{^}}tail_call_byval_align16:
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; GCN-NOT: s32
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; GCN-NOT: buffer_store_dword v33
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; GCN: buffer_store_dword v32, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
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; GCN-NOT: buffer_store_dword v33
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; GCN: buffer_store_dword v32, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
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; GCN: buffer_store_dword v33, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
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; GCN: buffer_load_dword v32, off, s[0:3], s32 offset:20
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; GCN: buffer_load_dword v33, off, s[0:3], s32 offset:16
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; GCN: s_getpc_b64
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; GCN: buffer_store_dword v32, off, s[0:3], s32 offset:4
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; GCN: buffer_load_dword v32, off, s[0:3], s32 offset:16
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; GCN: buffer_load_dword v32, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
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; GCN: buffer_store_dword v33, off, s[0:3], s32{{$}}
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; GCN: buffer_load_dword v33, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
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; GCN: buffer_load_dword v32, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
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; GCN-NOT: s32
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; GCN: s_setpc_b64
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define void @tail_call_byval_align16(<32 x i32> %val, double %tmp) #0 {
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@ -199,15 +199,14 @@ define amdgpu_kernel void @vload2_private(i16 addrspace(1)* nocapture readonly %
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v2, s4
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; GCN-NEXT: v_mov_b32_e32 v3, s5
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; GCN-NEXT: global_load_dword v4, v[2:3], off
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; GCN-NEXT: global_load_ushort v2, v[2:3], off offset:4
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; GCN-NEXT: global_load_ushort v4, v[2:3], off offset:4
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; GCN-NEXT: global_load_dword v2, v[2:3], off
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; GCN-NEXT: v_mov_b32_e32 v0, s6
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; GCN-NEXT: v_mov_b32_e32 v1, s7
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; GCN-NEXT: s_waitcnt vmcnt(1)
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; GCN-NEXT: buffer_store_short v4, off, s[0:3], s9 offset:4
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; GCN-NEXT: buffer_store_short_d16_hi v4, off, s[0:3], s9 offset:6
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; GCN-NEXT: s_waitcnt vmcnt(2)
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; GCN-NEXT: buffer_store_short v2, off, s[0:3], s9 offset:8
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: buffer_store_short v2, off, s[0:3], s9 offset:4
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; GCN-NEXT: buffer_store_short_d16_hi v2, off, s[0:3], s9 offset:6
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; GCN-NEXT: buffer_store_short v4, off, s[0:3], s9 offset:8
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; GCN-NEXT: buffer_load_ushort v2, off, s[0:3], s9 offset:4
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; GCN-NEXT: buffer_load_ushort v4, off, s[0:3], s9 offset:6
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; GCN-NEXT: s_waitcnt vmcnt(1)
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@ -236,19 +236,21 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned(<4 x float> addrspace(1)
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; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
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; VI-NEXT: v_add_u32_e32 v6, vcc, 1, v0
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; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
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; VI-NEXT: flat_load_ubyte v0, v[0:1]
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; VI-NEXT: flat_load_ubyte v1, v[6:7]
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; VI-NEXT: flat_load_ubyte v4, v[4:5]
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; VI-NEXT: flat_load_ubyte v2, v[2:3]
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; VI-NEXT: flat_load_ubyte v3, v[4:5]
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; VI-NEXT: flat_load_ubyte v4, v[6:7]
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; VI-NEXT: flat_load_ubyte v0, v[0:1]
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; VI-NEXT: s_waitcnt vmcnt(3) lgkmcnt(3)
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; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v2
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; VI-NEXT: s_waitcnt vmcnt(2) lgkmcnt(2)
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; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v1
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; VI-NEXT: v_or_b32_e32 v0, v1, v0
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; VI-NEXT: v_or_b32_e32 v1, v1, v3
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; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
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; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v4
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; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v1
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; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
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; VI-NEXT: v_or_b32_e32 v2, v2, v4
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; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2
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; VI-NEXT: v_or_b32_e32 v0, v2, v0
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; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v1
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; VI-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
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; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v2
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; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
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; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v3
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; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
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@ -414,35 +416,34 @@ define amdgpu_kernel void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias
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; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
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; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v0
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; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
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; VI-NEXT: flat_load_ubyte v9, v[2:3]
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; VI-NEXT: flat_load_ubyte v10, v[4:5]
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; VI-NEXT: flat_load_ubyte v11, v[2:3]
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; VI-NEXT: v_add_u32_e32 v2, vcc, 2, v0
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; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
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; VI-NEXT: v_add_u32_e32 v4, vcc, 5, v0
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; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
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; VI-NEXT: v_add_u32_e32 v6, vcc, 4, v0
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; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
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; VI-NEXT: v_add_u32_e32 v8, vcc, 6, v0
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; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
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; VI-NEXT: flat_load_ubyte v0, v[0:1]
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; VI-NEXT: flat_load_ubyte v1, v[8:9]
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; VI-NEXT: flat_load_ubyte v7, v[6:7]
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; VI-NEXT: flat_load_ubyte v4, v[4:5]
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; VI-NEXT: flat_load_ubyte v8, v[0:1]
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; VI-NEXT: v_add_u32_e32 v0, vcc, 6, v0
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: flat_load_ubyte v2, v[2:3]
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; VI-NEXT: flat_load_ubyte v3, v[4:5]
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; VI-NEXT: flat_load_ubyte v4, v[6:7]
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; VI-NEXT: flat_load_ubyte v0, v[0:1]
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; VI-NEXT: s_waitcnt vmcnt(6) lgkmcnt(6)
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; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v10
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; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v9
|
||||
; VI-NEXT: s_waitcnt vmcnt(5) lgkmcnt(5)
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v11
|
||||
; VI-NEXT: s_waitcnt vmcnt(4) lgkmcnt(4)
|
||||
; VI-NEXT: v_or_b32_e32 v0, v3, v0
|
||||
; VI-NEXT: s_waitcnt vmcnt(3) lgkmcnt(3)
|
||||
; VI-NEXT: v_cvt_f32_ubyte0_e32 v6, v1
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v10
|
||||
; VI-NEXT: s_waitcnt vmcnt(2) lgkmcnt(2)
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
|
||||
; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
|
||||
; VI-NEXT: v_or_b32_e32 v4, v3, v4
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_cvt_f32_ubyte0_e32 v6, v0
|
||||
; VI-NEXT: v_or_b32_e32 v0, v1, v8
|
||||
; VI-NEXT: v_or_b32_sdwa v1, v5, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
||||
; VI-NEXT: v_or_b32_e32 v0, v1, v0
|
||||
; VI-NEXT: v_or_b32_e32 v4, v4, v7
|
||||
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
|
||||
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
||||
; VI-NEXT: v_cvt_f32_ubyte1_e32 v5, v4
|
||||
|
|
@ -699,23 +700,24 @@ define amdgpu_kernel void @v4i8_zext_v4i32_to_v4f32(<4 x float> addrspace(1)* no
|
|||
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
|
||||
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v0
|
||||
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
|
||||
; VI-NEXT: v_add_u32_e32 v6, vcc, 2, v0
|
||||
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
|
||||
; VI-NEXT: flat_load_ubyte v0, v[0:1]
|
||||
; VI-NEXT: flat_load_ubyte v1, v[6:7]
|
||||
; VI-NEXT: flat_load_ubyte v4, v[4:5]
|
||||
; VI-NEXT: flat_load_ubyte v6, v[0:1]
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
||||
; VI-NEXT: flat_load_ubyte v2, v[2:3]
|
||||
; VI-NEXT: flat_load_ubyte v3, v[4:5]
|
||||
; VI-NEXT: flat_load_ubyte v0, v[0:1]
|
||||
; VI-NEXT: s_waitcnt vmcnt(2) lgkmcnt(2)
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v1, 8, v2
|
||||
; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v4
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v3
|
||||
; VI-NEXT: v_or_b32_e32 v1, v1, v6
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
||||
; VI-NEXT: v_or_b32_e32 v4, v2, v0
|
||||
; VI-NEXT: v_or_b32_sdwa v0, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
||||
; VI-NEXT: v_or_b32_e32 v0, v0, v4
|
||||
; VI-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
||||
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
||||
; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
|
||||
; VI-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
|
||||
; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
|
||||
; VI-NEXT: v_cvt_f32_ubyte1_e32 v1, v4
|
||||
; VI-NEXT: v_cvt_f32_ubyte1_e32 v1, v1
|
||||
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
|
||||
; VI-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
||||
|
|
|
|||
|
|
@ -473,8 +473,8 @@ define amdgpu_kernel void @load_constant_disjoint_offsets(i32 addrspace(1)* %out
|
|||
; GFX9-NOT: m0
|
||||
|
||||
; GCN-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], bar@abs32@lo{{$}}
|
||||
; GCN: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[PTR]] offset1:1
|
||||
; GCN: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[PTR]] offset0:2 offset1:3
|
||||
; GCN: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[PTR]] offset1:1
|
||||
define amdgpu_kernel void @load_misaligned64_constant_offsets(i64 addrspace(1)* %out) {
|
||||
%val0 = load i64, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 0), align 4
|
||||
%val1 = load i64, i64 addrspace(3)* getelementptr inbounds ([4 x i64], [4 x i64] addrspace(3)* @bar, i32 0, i32 1), align 4
|
||||
|
|
|
|||
|
|
@ -231,10 +231,10 @@ declare void @func(<4 x float> addrspace(5)* nocapture) #0
|
|||
|
||||
; GCN-LABEL: {{^}}undefined_stack_store_reg:
|
||||
; GCN: s_and_saveexec_b64
|
||||
; GCN: buffer_store_dword v0, off, s[0:3], s34 offset:
|
||||
; GCN: buffer_store_dword v0, off, s[0:3], s34 offset:
|
||||
; GCN: buffer_store_dword v0, off, s[0:3], s34 offset:
|
||||
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s34 offset:
|
||||
; GCN: buffer_store_dword v0, off, s[0:3], s34 offset:
|
||||
; GCN: buffer_store_dword v0, off, s[0:3], s34 offset:
|
||||
; GCN: buffer_store_dword v0, off, s[0:3], s34 offset:
|
||||
define void @undefined_stack_store_reg(float %arg, i32 %arg1) #0 {
|
||||
bb:
|
||||
%tmp = alloca <4 x float>, align 16, addrspace(5)
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@
|
|||
; an unused stack slot, causing ScratchSize to be non-zero.
|
||||
|
||||
; GCN-LABEL: store_v3i32:
|
||||
; GCN: ds_read_b64
|
||||
; GCN: ds_read_b32
|
||||
; GCN: ds_read_b64
|
||||
; GCN: ds_write_b32
|
||||
; GCN: ds_write_b64
|
||||
; GCN: ScratchSize: 0
|
||||
|
|
@ -17,8 +17,8 @@ define amdgpu_kernel void @store_v3i32(<3 x i32> addrspace(3)* %out, <3 x i32> %
|
|||
}
|
||||
|
||||
; GCN-LABEL: store_v5i32:
|
||||
; GCN: ds_read2_b64
|
||||
; GCN: ds_read_b32
|
||||
; GCN: ds_read2_b64
|
||||
; GCN: ds_write_b32
|
||||
; GCN: ds_write2_b64
|
||||
; GCN: ScratchSize: 0
|
||||
|
|
|
|||
|
|
@ -1642,10 +1642,10 @@ define amdgpu_kernel void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)
|
|||
; SI-NEXT: v_mov_b32_e32 v13, s21
|
||||
; SI-NEXT: v_mov_b32_e32 v14, s22
|
||||
; SI-NEXT: v_mov_b32_e32 v15, s23
|
||||
; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], s7 offset:96
|
||||
; SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], s7 offset:112
|
||||
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], s7 offset:64
|
||||
; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], s7 offset:96
|
||||
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], s7 offset:80
|
||||
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], s7 offset:64
|
||||
; SI-NEXT: v_or_b32_e32 v16, s4, v16
|
||||
; SI-NEXT: v_mov_b32_e32 v0, 0
|
||||
; SI-NEXT: v_mov_b32_e32 v1, 0x40200000
|
||||
|
|
@ -1688,10 +1688,10 @@ define amdgpu_kernel void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)
|
|||
; VI-NEXT: v_mov_b32_e32 v13, s21
|
||||
; VI-NEXT: v_mov_b32_e32 v14, s22
|
||||
; VI-NEXT: v_mov_b32_e32 v15, s23
|
||||
; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], s7 offset:96
|
||||
; VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], s7 offset:112
|
||||
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], s7 offset:64
|
||||
; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], s7 offset:96
|
||||
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], s7 offset:80
|
||||
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], s7 offset:64
|
||||
; VI-NEXT: v_or_b32_e32 v16, s4, v16
|
||||
; VI-NEXT: v_mov_b32_e32 v0, 0
|
||||
; VI-NEXT: v_mov_b32_e32 v1, 0x40200000
|
||||
|
|
|
|||
|
|
@ -855,8 +855,8 @@ define amdgpu_kernel void @struct_argument_alignment({i32, i64} %arg0, i8, {i32,
|
|||
; multiple.
|
||||
; FUNC-LABEL: {{^}}packed_struct_argument_alignment:
|
||||
; HSA-GFX9: kernarg_segment_byte_size = 28
|
||||
; HSA-GFX9: global_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:13
|
||||
; HSA-GFX9: global_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:17
|
||||
; HSA-GFX9: global_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:13
|
||||
; HSA-GFX9: s_load_dword s{{[0-9]+}}, s[4:5], 0x0
|
||||
; HSA-GFX9: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x4
|
||||
define amdgpu_kernel void @packed_struct_argument_alignment(<{i32, i64}> %arg0, i8, <{i32, i64}> %arg1) {
|
||||
|
|
|
|||
|
|
@ -75,8 +75,8 @@ define amdgpu_kernel void @struct_argument_alignment({i32, i64} %arg0, i8, {i32,
|
|||
; multiple.
|
||||
; FUNC-LABEL: {{^}}packed_struct_argument_alignment:
|
||||
; HSA-VI: kernarg_segment_byte_size = 28
|
||||
; HSA-VI: global_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:13
|
||||
; HSA-VI: global_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:17
|
||||
; HSA-VI: global_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, off offset:13
|
||||
; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x0
|
||||
; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x4
|
||||
define amdgpu_kernel void @packed_struct_argument_alignment(<{i32, i64}> %arg0, i8, <{i32, i64}> %arg1) {
|
||||
|
|
|
|||
|
|
@ -137,22 +137,22 @@ define amdgpu_kernel void @v_test_imax_sge_v3i16(<3 x i16> addrspace(1)* %out, <
|
|||
; VI-NEXT: v_mov_b32_e32 v7, s5
|
||||
; VI-NEXT: v_add_u32_e32 v6, vcc, s4, v6
|
||||
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
|
||||
; VI-NEXT: flat_load_dword v8, v[0:1]
|
||||
; VI-NEXT: flat_load_ushort v9, v[4:5]
|
||||
; VI-NEXT: flat_load_ushort v8, v[4:5]
|
||||
; VI-NEXT: flat_load_dword v9, v[0:1]
|
||||
; VI-NEXT: v_add_u32_e32 v0, vcc, 4, v2
|
||||
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
|
||||
; VI-NEXT: flat_load_dword v2, v[2:3]
|
||||
; VI-NEXT: flat_load_ushort v0, v[0:1]
|
||||
; VI-NEXT: flat_load_dword v1, v[2:3]
|
||||
; VI-NEXT: v_add_u32_e32 v4, vcc, 4, v6
|
||||
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
|
||||
; VI-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
|
||||
; VI-NEXT: v_max_i16_e32 v1, v8, v2
|
||||
; VI-NEXT: v_max_i16_sdwa v2, v8, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
||||
; VI-NEXT: v_max_i16_e32 v0, v8, v0
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_max_i16_e32 v0, v9, v0
|
||||
; VI-NEXT: flat_store_dword v[6:7], v1
|
||||
; VI-NEXT: v_max_i16_e32 v2, v9, v1
|
||||
; VI-NEXT: v_max_i16_sdwa v1, v9, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
||||
; VI-NEXT: v_or_b32_e32 v1, v2, v1
|
||||
; VI-NEXT: flat_store_short v[4:5], v0
|
||||
; VI-NEXT: flat_store_dword v[6:7], v1
|
||||
; VI-NEXT: s_endpgm
|
||||
;
|
||||
; GFX9-LABEL: v_test_imax_sge_v3i16:
|
||||
|
|
|
|||
|
|
@ -221,26 +221,26 @@ define amdgpu_kernel void @Address32(i8 addrspace(1)* %buffer) {
|
|||
; GFX8: flat_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
|
||||
;
|
||||
; GFX9: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:1024
|
||||
; GFX9: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
; GFX9: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:1024
|
||||
; GFX9: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:2048
|
||||
; GFX9: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:3072
|
||||
; GFX9: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
; GFX9: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:1024
|
||||
; GFX9: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
; GFX9: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:1024
|
||||
; GFX9: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:2048
|
||||
; GFX9: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:3072
|
||||
; GFX9: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
;
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:1024
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:1024
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:-2048
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:1024
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:1024
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:1024
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:1024
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:-2048
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:1024
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:1024
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:1024
|
||||
entry:
|
||||
%call = tail call i64 @_Z13get_global_idj(i32 0)
|
||||
%conv = and i64 %call, 255
|
||||
|
|
@ -299,10 +299,10 @@ define amdgpu_kernel void @Offset64(i8 addrspace(1)* %buffer) {
|
|||
; GFX8: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
|
||||
; GFX8: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
|
||||
;
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:2048
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-4096
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:2048
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
;
|
||||
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
|
||||
|
|
@ -352,8 +352,8 @@ define amdgpu_kernel void @p32Offset64(i8 addrspace(1)* %buffer) {
|
|||
;
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:-2048
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:1024
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
; GFX10: global_load_dword {{v[0-9]+}}, v[{{[0-9]+:[0-9]+}}], off offset:1024
|
||||
entry:
|
||||
%call = tail call i64 @_Z13get_global_idj(i32 0)
|
||||
%conv = and i64 %call, 255
|
||||
|
|
@ -454,13 +454,13 @@ define amdgpu_kernel void @ReverseOrder(i8 addrspace(1)* %buffer) {
|
|||
; GFX8: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
|
||||
; GFX8: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
|
||||
;
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:2048
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:2048
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:2048
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:2048
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:2048
|
||||
;
|
||||
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
|
||||
|
|
@ -519,8 +519,8 @@ define hidden amdgpu_kernel void @negativeoffset(i8 addrspace(1)* nocapture %buf
|
|||
; GFX8: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
|
||||
; GFX8: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
|
||||
;
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:2048
|
||||
; GFX9: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off
|
||||
;
|
||||
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
|
||||
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off
|
||||
|
|
|
|||
|
|
@ -509,8 +509,8 @@ define amdgpu_kernel void @s_shl_v2i128ss(<2 x i128> %lhs, <2 x i128> %rhs) {
|
|||
; GCN-NEXT: v_mov_b32_e32 v10, 16
|
||||
; GCN-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
|
||||
; GCN-NEXT: v_mov_b32_e32 v11, 0
|
||||
; GCN-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
|
||||
; GCN-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
|
||||
; GCN-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
|
||||
; GCN-NEXT: s_endpgm
|
||||
%shift = shl <2 x i128> %lhs, %rhs
|
||||
store <2 x i128> %shift, <2 x i128> addrspace(1)* null
|
||||
|
|
@ -579,8 +579,8 @@ define amdgpu_kernel void @s_lshr_v2i128_ss(<2 x i128> %lhs, <2 x i128> %rhs) {
|
|||
; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[0:1]
|
||||
; GCN-NEXT: v_mov_b32_e32 v10, 16
|
||||
; GCN-NEXT: v_mov_b32_e32 v11, 0
|
||||
; GCN-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
|
||||
; GCN-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
|
||||
; GCN-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
|
||||
; GCN-NEXT: s_endpgm
|
||||
%shift = lshr <2 x i128> %lhs, %rhs
|
||||
store <2 x i128> %shift, <2 x i128> addrspace(1)* null
|
||||
|
|
@ -653,8 +653,8 @@ define amdgpu_kernel void @s_ashr_v2i128_ss(<2 x i128> %lhs, <2 x i128> %rhs) {
|
|||
; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[0:1]
|
||||
; GCN-NEXT: v_mov_b32_e32 v10, 16
|
||||
; GCN-NEXT: v_mov_b32_e32 v11, 0
|
||||
; GCN-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
|
||||
; GCN-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
|
||||
; GCN-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
|
||||
; GCN-NEXT: s_endpgm
|
||||
%shift = ashr <2 x i128> %lhs, %rhs
|
||||
store <2 x i128> %shift, <2 x i128> addrspace(1)* null
|
||||
|
|
|
|||
|
|
@ -10,21 +10,20 @@ define void @vgpr_descriptor_waterfall_loop_idom_update(<4 x i32>* %arg) {
|
|||
; GCN-NEXT: BB0_1: ; %bb0
|
||||
; GCN-NEXT: ; =>This Loop Header: Depth=1
|
||||
; GCN-NEXT: ; Child Loop BB0_2 Depth 2
|
||||
; GCN-NEXT: v_add_co_u32_e64 v4, vcc_lo, v0, 8
|
||||
; GCN-NEXT: v_add_co_u32_e64 v2, vcc_lo, v0, 8
|
||||
; GCN-NEXT: s_mov_b32 s5, exec_lo
|
||||
; GCN-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
|
||||
; GCN-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
|
||||
; GCN-NEXT: flat_load_dwordx2 v[4:5], v[4:5]
|
||||
; GCN-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
|
||||
; GCN-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
|
||||
; GCN-NEXT: flat_load_dwordx2 v[4:5], v[0:1]
|
||||
; GCN-NEXT: BB0_2: ; Parent Loop BB0_1 Depth=1
|
||||
; GCN-NEXT: ; => This Inner Loop Header: Depth=2
|
||||
; GCN-NEXT: s_waitcnt vmcnt(1) lgkmcnt(1)
|
||||
; GCN-NEXT: v_readfirstlane_b32 s8, v2
|
||||
; GCN-NEXT: v_readfirstlane_b32 s9, v3
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; GCN-NEXT: v_readfirstlane_b32 s10, v4
|
||||
; GCN-NEXT: v_readfirstlane_b32 s11, v5
|
||||
; GCN-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[2:3]
|
||||
; GCN-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[4:5]
|
||||
; GCN-NEXT: v_readfirstlane_b32 s8, v4
|
||||
; GCN-NEXT: v_readfirstlane_b32 s9, v5
|
||||
; GCN-NEXT: v_readfirstlane_b32 s10, v2
|
||||
; GCN-NEXT: v_readfirstlane_b32 s11, v3
|
||||
; GCN-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[8:9], v[4:5]
|
||||
; GCN-NEXT: v_cmp_eq_u64_e64 s4, s[10:11], v[2:3]
|
||||
; GCN-NEXT: s_and_b32 s4, vcc_lo, s4
|
||||
; GCN-NEXT: s_and_saveexec_b32 s4, s4
|
||||
; GCN-NEXT: s_nop 0
|
||||
|
|
|
|||
Loading…
Reference in New Issue