forked from OSchip/llvm-project
[DAGCombiner] give names to repeated calcs in isAlias(); NFCI
llvm-svn: 300850
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@ -16099,9 +16099,11 @@ bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const {
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Base2, Offset2, GV2, CV2);
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// If they have a same base address then check to see if they overlap.
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unsigned NumBytes0 = Op0->getMemoryVT().getSizeInBits() >> 3;
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unsigned NumBytes1 = Op1->getMemoryVT().getSizeInBits() >> 3;
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if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
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return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
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(Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
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return !((Offset1 + NumBytes0) <= Offset2 ||
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(Offset2 + NumBytes1) <= Offset1);
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// It is possible for different frame indices to alias each other, mostly
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// when tail call optimization reuses return address slots for arguments.
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@ -16111,8 +16113,8 @@ bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const {
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MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
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Offset1 += MFI.getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
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Offset2 += MFI.getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
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return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
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(Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
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return !((Offset1 + NumBytes0) <= Offset2 ||
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(Offset2 + NumBytes1) <= Offset1);
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}
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// Otherwise, if we know what the bases are, and they aren't identical, then
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@ -16126,16 +16128,14 @@ bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const {
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// splitting vector types.
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if ((Op0->getOriginalAlignment() == Op1->getOriginalAlignment()) &&
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(Op0->getSrcValueOffset() != Op1->getSrcValueOffset()) &&
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(Op0->getMemoryVT().getSizeInBits() >> 3 ==
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Op1->getMemoryVT().getSizeInBits() >> 3) &&
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(Op0->getOriginalAlignment() > (Op0->getMemoryVT().getSizeInBits() >> 3))) {
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(NumBytes0 == NumBytes1) && (Op0->getOriginalAlignment() > NumBytes0)) {
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int64_t OffAlign1 = Op0->getSrcValueOffset() % Op0->getOriginalAlignment();
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int64_t OffAlign2 = Op1->getSrcValueOffset() % Op1->getOriginalAlignment();
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// There is no overlap between these relatively aligned accesses of similar
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// size, return no alias.
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if ((OffAlign1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign2 ||
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(OffAlign2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign1)
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if ((OffAlign1 + NumBytes0) <= OffAlign2 ||
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(OffAlign2 + NumBytes1) <= OffAlign1)
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return false;
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}
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@ -16152,10 +16152,8 @@ bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const {
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// Use alias analysis information.
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int64_t MinOffset = std::min(Op0->getSrcValueOffset(),
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Op1->getSrcValueOffset());
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int64_t Overlap1 = (Op0->getMemoryVT().getSizeInBits() >> 3) +
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Op0->getSrcValueOffset() - MinOffset;
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int64_t Overlap2 = (Op1->getMemoryVT().getSizeInBits() >> 3) +
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Op1->getSrcValueOffset() - MinOffset;
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int64_t Overlap1 = NumBytes0 + Op0->getSrcValueOffset() - MinOffset;
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int64_t Overlap2 = NumBytes1 + Op1->getSrcValueOffset() - MinOffset;
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AliasResult AAResult =
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AA.alias(MemoryLocation(Op0->getMemOperand()->getValue(), Overlap1,
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UseTBAA ? Op0->getAAInfo() : AAMDNodes()),
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