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Fix a Cygwin build failure caused by enum values starting with '_', which is conflicted with some platform macros. 

This solution only renames variables, no functional change.

NOTE: This is a candidate for the 3.4 branch.
llvm-svn: 195421
This commit is contained in:
Hao Liu 2013-11-22 08:17:16 +00:00
parent 9ba7536e45
commit b75d80fdf0
4 changed files with 44 additions and 44 deletions
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4
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
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@ -261,12 +261,12 @@ multiclass VectorList_operands<string PREFIX, string LAYOUT, int Count,
let Name = PREFIX # LAYOUT # Count; let Name = PREFIX # LAYOUT # Count;
let RenderMethod = "addVectorListOperands"; let RenderMethod = "addVectorListOperands";
let PredicateMethod = let PredicateMethod =
"isVectorList<A64Layout::_" # LAYOUT # ", " # Count # ">"; "isVectorList<A64Layout::VL_" # LAYOUT # ", " # Count # ">";
let ParserMethod = "ParseVectorList"; let ParserMethod = "ParseVectorList";
} }
def _operand : RegisterOperand<RegList, def _operand : RegisterOperand<RegList,
"printVectorList<A64Layout::_" # LAYOUT # ", " # Count # ">"> { "printVectorList<A64Layout::VL_" # LAYOUT # ", " # Count # ">"> {
let ParserMatchClass = let ParserMatchClass =
!cast<AsmOperandClass>(PREFIX # LAYOUT # "_asmoperand"); !cast<AsmOperandClass>(PREFIX # LAYOUT # "_asmoperand");
} }

10
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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@ -2066,7 +2066,7 @@ AArch64AsmParser::OperandMatchResultTy AArch64AsmParser::ParseVectorList(
A64Layout::VectorLayout Layout = A64StringToVectorLayout(LayoutStr); A64Layout::VectorLayout Layout = A64StringToVectorLayout(LayoutStr);
if (Count > 1) { // If count > 1, create vector list using super register. if (Count > 1) { // If count > 1, create vector list using super register.
bool IsVec64 = (Layout < A64Layout::_16B); bool IsVec64 = (Layout < A64Layout::VL_16B);
static unsigned SupRegIDs[3][2] = { static unsigned SupRegIDs[3][2] = {
{ AArch64::QPairRegClassID, AArch64::DPairRegClassID }, { AArch64::QPairRegClassID, AArch64::DPairRegClassID },
{ AArch64::QTripleRegClassID, AArch64::DTripleRegClassID }, { AArch64::QTripleRegClassID, AArch64::DTripleRegClassID },
@ -2084,10 +2084,10 @@ AArch64AsmParser::OperandMatchResultTy AArch64AsmParser::ParseVectorList(
if (Parser.getTok().is(AsmToken::LBrac)) { if (Parser.getTok().is(AsmToken::LBrac)) {
uint32_t NumLanes = 0; uint32_t NumLanes = 0;
switch(Layout) { switch(Layout) {
case A64Layout::_B : NumLanes = 16; break; case A64Layout::VL_B : NumLanes = 16; break;
case A64Layout::_H : NumLanes = 8; break; case A64Layout::VL_H : NumLanes = 8; break;
case A64Layout::_S : NumLanes = 4; break; case A64Layout::VL_S : NumLanes = 4; break;
case A64Layout::_D : NumLanes = 2; break; case A64Layout::VL_D : NumLanes = 2; break;
default: default:
SMLoc Loc = getLexer().getLoc(); SMLoc Loc = getLexer().getLoc();
Error(Loc, "expected comma before next operand"); Error(Loc, "expected comma before next operand");

2
llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
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@ -521,7 +521,7 @@ void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
std::string LayoutStr = A64VectorLayoutToString(Layout); std::string LayoutStr = A64VectorLayoutToString(Layout);
O << "{"; O << "{";
if (Count > 1) { // Print sub registers separately if (Count > 1) { // Print sub registers separately
bool IsVec64 = (Layout < A64Layout::_16B); bool IsVec64 = (Layout < A64Layout::VL_16B);
unsigned SubRegIdx = IsVec64 ? AArch64::dsub_0 : AArch64::qsub_0; unsigned SubRegIdx = IsVec64 ? AArch64::dsub_0 : AArch64::qsub_0;
for (unsigned I = 0; I < Count; I++) { for (unsigned I = 0; I < Count; I++) {
std::string Name = getRegisterName(MRI.getSubReg(Reg, SubRegIdx++)); std::string Name = getRegisterName(MRI.getSubReg(Reg, SubRegIdx++));

72
llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
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@ -309,40 +309,40 @@ namespace A64SE {
namespace A64Layout { namespace A64Layout {
enum VectorLayout { enum VectorLayout {
Invalid = -1, Invalid = -1,
_8B, VL_8B,
_4H, VL_4H,
_2S, VL_2S,
_1D, VL_1D,
_16B, VL_16B,
_8H, VL_8H,
_4S, VL_4S,
_2D, VL_2D,
// Bare layout for the 128-bit vector // Bare layout for the 128-bit vector
// (only show ".b", ".h", ".s", ".d" without vector number) // (only show ".b", ".h", ".s", ".d" without vector number)
_B, VL_B,
_H, VL_H,
_S, VL_S,
_D VL_D
}; };
} }
inline static const char * inline static const char *
A64VectorLayoutToString(A64Layout::VectorLayout Layout) { A64VectorLayoutToString(A64Layout::VectorLayout Layout) {
switch (Layout) { switch (Layout) {
case A64Layout::_8B: return ".8b"; case A64Layout::VL_8B: return ".8b";
case A64Layout::_4H: return ".4h"; case A64Layout::VL_4H: return ".4h";
case A64Layout::_2S: return ".2s"; case A64Layout::VL_2S: return ".2s";
case A64Layout::_1D: return ".1d"; case A64Layout::VL_1D: return ".1d";
case A64Layout::_16B: return ".16b"; case A64Layout::VL_16B: return ".16b";
case A64Layout::_8H: return ".8h"; case A64Layout::VL_8H: return ".8h";
case A64Layout::_4S: return ".4s"; case A64Layout::VL_4S: return ".4s";
case A64Layout::_2D: return ".2d"; case A64Layout::VL_2D: return ".2d";
case A64Layout::_B: return ".b"; case A64Layout::VL_B: return ".b";
case A64Layout::_H: return ".h"; case A64Layout::VL_H: return ".h";
case A64Layout::_S: return ".s"; case A64Layout::VL_S: return ".s";
case A64Layout::_D: return ".d"; case A64Layout::VL_D: return ".d";
default: llvm_unreachable("Unknown Vector Layout"); default: llvm_unreachable("Unknown Vector Layout");
} }
} }
@ -350,18 +350,18 @@ A64VectorLayoutToString(A64Layout::VectorLayout Layout) {
inline static A64Layout::VectorLayout inline static A64Layout::VectorLayout
A64StringToVectorLayout(StringRef LayoutStr) { A64StringToVectorLayout(StringRef LayoutStr) {
return StringSwitch<A64Layout::VectorLayout>(LayoutStr) return StringSwitch<A64Layout::VectorLayout>(LayoutStr)
.Case(".8b", A64Layout::_8B) .Case(".8b", A64Layout::VL_8B)
.Case(".4h", A64Layout::_4H) .Case(".4h", A64Layout::VL_4H)
.Case(".2s", A64Layout::_2S) .Case(".2s", A64Layout::VL_2S)
.Case(".1d", A64Layout::_1D) .Case(".1d", A64Layout::VL_1D)
.Case(".16b", A64Layout::_16B) .Case(".16b", A64Layout::VL_16B)
.Case(".8h", A64Layout::_8H) .Case(".8h", A64Layout::VL_8H)
.Case(".4s", A64Layout::_4S) .Case(".4s", A64Layout::VL_4S)
.Case(".2d", A64Layout::_2D) .Case(".2d", A64Layout::VL_2D)
.Case(".b", A64Layout::_B) .Case(".b", A64Layout::VL_B)
.Case(".h", A64Layout::_H) .Case(".h", A64Layout::VL_H)
.Case(".s", A64Layout::_S) .Case(".s", A64Layout::VL_S)
.Case(".d", A64Layout::_D) .Case(".d", A64Layout::VL_D)
.Default(A64Layout::Invalid); .Default(A64Layout::Invalid);
} }